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2024-04-25 - 14:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Apr 25, 2024 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2741521250,6sleep32819699cyclictest20:25:293
8255911210,93ptp4l401ktimersoftd/319:09:513
275742847,19sleep00-21swapper/019:05:470
220992790,2sleep20-21swapper/222:30:302
277722744,18sleep20-21swapper/219:08:152
825591720,2ptp4l401ktimersoftd/320:55:113
825591720,2ptp4l401ktimersoftd/320:55:113
56482670,6sleep15647-21basename20:50:001
825591640,1ptp4l401ktimersoftd/322:46:273
825591630,1ptp4l401ktimersoftd/321:11:343
28195996053,4cyclictest33-21ksoftirqd/221:40:132
28195996053,4cyclictest33-21ksoftirqd/200:30:102
825591590,1ptp4l401ktimersoftd/323:04:563
28195995952,4cyclictest33-21ksoftirqd/219:10:102
28195995750,4cyclictest33-21ksoftirqd/223:40:102
825591560,2ptp4l391rcuc/323:57:383
28195995548,4cyclictest33-21ksoftirqd/200:00:122
28195995510,7cyclictest33-21ksoftirqd/223:40:002
825591540,3ptp4l401ktimersoftd/319:10:003
28195995447,4cyclictest33-21ksoftirqd/222:55:102
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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