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2023-10-03 - 15:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Oct 03, 2023 12:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8255911700,5ptp4l401ktimersoftd/307:06:533
330721670,8sleep1297999cyclictest07:10:221
1806521620,3sleep20-21swapper/208:50:272
2395821390,9sleep0297899cyclictest11:20:290
511421160,5sleep05118-21irqrtprio10:40:260
1623021150,8sleep0297899cyclictest08:45:320
2871321120,2sleep30-21swapper/311:30:273
3242221010,3sleep00-21swapper/011:40:010
2978998125,10cyclictest9-21ksoftirqd/010:55:260
24832804,19sleep10-21swapper/107:07:251
2981997972,4cyclictest41-21ksoftirqd/307:45:203
2978997927,11cyclictest9-21ksoftirqd/009:25:250
2978997831,6cyclictest9-21ksoftirqd/007:55:270
24102778,17sleep00-21swapper/007:06:300
2981997669,4cyclictest41-21ksoftirqd/312:20:193
2981997669,4cyclictest41-21ksoftirqd/309:25:173
2981997568,4cyclictest41-21ksoftirqd/310:20:213
2981997467,3cyclictest41-21ksoftirqd/311:15:193
2981997466,5cyclictest41-21ksoftirqd/311:20:203
2981997466,4cyclictest41-21ksoftirqd/307:20:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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