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2025-07-06 - 02:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 05, 2025 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
323412235169,22sleep30-21swapper/307:09:053
323662205171,23sleep10-21swapper/107:09:231
323432203170,22sleep00-21swapper/007:09:060
321602201168,22sleep20-21swapper/207:06:422
137191167124,13phc2sys0-21swapper/307:10:013
137191167124,13phc2sys0-21swapper/307:10:013
1150721660,4sleep03271099cyclictest10:50:290
135692630,2sleep00-21swapper/012:05:150
32712995515,38cyclictest19996-21kworker/2:010:25:472
136991550,1ptp4l401ktimersoftd/311:05:213
3271299521,3cyclictest3391-21kworker/2:112:00:272
3271299491,46cyclictest27698-21kworker/2:207:35:272
26912490,1sleep20-21swapper/207:15:002
26912490,1sleep20-21swapper/207:15:002
32711994639,4cyclictest8697-21ls08:35:011
3271299452,41cyclictest3391-21kworker/2:112:33:272
3271299450,43cyclictest0-21swapper/209:00:282
3271299450,43cyclictest0-21swapper/209:00:282
132891450,4getstats41-21ksoftirqd/308:37:503
3271299428,4cyclictest78502grep10:45:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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