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2021-08-04 - 21:49

Intel(R) Celeron(R) CPU G1820 @ 2.70GHz, Linux 3.18.40-rt42 (Profile)

Latency plot of system in rack #a, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot8.osadl.org (updated Fri Jun 25, 2021 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
368323017,11sleep00-21swapper/019:05:360
317922815,11sleep10-21swapper/119:05:171
414599268,17cyclictest0-21swapper/019:54:360
414599260,25cyclictest0-21swapper/022:59:550
414599260,25cyclictest0-21swapper/022:25:160
414599250,24cyclictest0-21swapper/021:50:060
414599250,1cyclictest0-21swapper/021:11:160
414599240,24cyclictest0-21swapper/023:45:150
414699235,8cyclictest0-21swapper/120:18:591
414699230,14cyclictest0-21swapper/120:59:591
414599231,12cyclictest0-21swapper/022:36:590
414599230,23cyclictest0-21swapper/022:17:360
414599227,8cyclictest0-21swapper/022:53:590
414599220,9cyclictest0-21swapper/023:57:000
414599220,17cyclictest0-21swapper/019:21:590
414699214,11cyclictest0-21swapper/120:32:591
414699213,17cyclictest14590-21kworker/1:122:26:161
414599214,13cyclictest0-21swapper/019:39:590
414599211,9cyclictest0-21swapper/023:11:000
414599210,12cyclictest0-21swapper/021:09:590
414699205,8cyclictest0-21swapper/119:27:581
414699204,7cyclictest0-21swapper/122:45:591
414699200,16cyclictest0-21swapper/121:34:001
4145992017,2cyclictest0-21swapper/023:35:580
414599200,0cyclictest0-21swapper/021:18:540
414699190,1cyclictest7946-21diskstats00:15:171
414599190,9cyclictest0-21swapper/023:16:590
414599190,2cyclictest0-21swapper/021:44:560
414599190,17cyclictest0-21swapper/021:36:000
4145991815,2cyclictest0-21swapper/023:07:590
414699173,8cyclictest0-21swapper/122:40:591
414599175,6cyclictest0-21swapper/020:53:590
414599175,6cyclictest0-21swapper/019:48:000
4145991715,1cyclictest12977-21ssh21:29:000
414599170,9cyclictest0-21swapper/000:27:590
414599170,7cyclictest0-21swapper/023:29:590
414699164,7cyclictest0-21swapper/120:50:591
414699164,7cyclictest0-21swapper/119:14:581
414699160,16cyclictest0-21swapper/121:42:381
414699160,0cyclictest0-21swapper/123:43:591
414599164,11cyclictest0-21swapper/020:34:590
414599163,5cyclictest0-21swapper/020:46:590
4145991613,2cyclictest0-21swapper/023:02:590
414599160,16cyclictest0-21swapper/023:31:360
414699152,7cyclictest0-21swapper/119:19:591
414699152,10cyclictest0-21swapper/119:41:581
414599155,4cyclictest0-21swapper/019:59:590
4145991513,1cyclictest0-21swapper/021:33:000
414599150,15cyclictest0-21swapper/000:31:460
414699143,5cyclictest0-21swapper/120:49:591
414699143,10cyclictest0-21swapper/123:59:001
414599143,9cyclictest19698-21ssh00:22:590
4145991412,1cyclictest0-21swapper/022:23:000
4145991410,3cyclictest0-21swapper/021:46:590
414599140,9cyclictest0-21swapper/022:44:590
414699134,5cyclictest0-21swapper/120:08:591
414699134,2cyclictest26634-21ssh23:23:591
414699131,7cyclictest0-21swapper/121:39:591
414699131,11cyclictest135350irq/39-eth1-tx-22:35:271
414599132,7cyclictest5590-21ssh22:05:590
414599132,4cyclictest0-21swapper/020:42:000
4145991311,1cyclictest0-21swapper/020:00:590
4145991311,1cyclictest0-21swapper/019:45:000
414699126,5cyclictest0-21swapper/120:28:591
414699123,5cyclictest27594-21ssh21:59:591
414699122,5cyclictest0-21swapper/120:22:591
414599124,4cyclictest0-21swapper/020:06:590
4145991210,1cyclictest0-21swapper/022:15:000
4145991210,1cyclictest0-21swapper/000:02:430
414699119,1cyclictest0-21swapper/122:10:591
414699119,1cyclictest0-21swapper/100:38:581
414699118,2cyclictest0-21swapper/123:52:591
414699116,5cyclictest0-21swapper/121:54:591
414699112,6cyclictest29907-21ssh23:46:591
414699112,4cyclictest0-21swapper/121:21:591
4146991110,1cyclictest0-21swapper/119:51:361
414699110,0cyclictest0-21swapper/119:32:561
414699110,0cyclictest0-21swapper/100:23:051
414599119,1cyclictest0-21swapper/021:22:590
414599116,4cyclictest0-21swapper/020:19:590
414599114,6cyclictest1824-21ssh00:10:590
414599113,2cyclictest2133-21compiz21:59:590
414599112,1cyclictest0-21swapper/020:12:590
414599111,5cyclictest8311-21ping19:28:590
414599110,6cyclictest0-21swapper/020:25:590
414599110,1cyclictest0-21swapper/020:55:330
414599110,1cyclictest0-21swapper/019:14:330
414699108,1cyclictest0-21swapper/100:34:591
414699105,3cyclictest0-21swapper/119:49:001
414699102,4cyclictest0-21swapper/120:43:001
414699102,4cyclictest0-21swapper/120:10:591
414699102,4cyclictest0-21swapper/120:03:591
4146991010,0cyclictest0-21swapper/119:20:061
414699100,10cyclictest0-21swapper/121:47:151
414699100,0cyclictest0-21swapper/123:04:161
414599108,1cyclictest0-21swapper/023:51:590
414599108,1cyclictest0-21swapper/022:01:590
414599107,2cyclictest0-21swapper/021:01:580
414599107,2cyclictest0-21swapper/000:35:590
414599103,5cyclictest0-21swapper/023:40:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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