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2024-12-10 - 17:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Tue Dec 10, 2024 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
91099199472410,1cyclictest1743409-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
00:06:213
9109799945226,424cyclictest0-21swapper/200:27:578
9109909944948,400cyclictest3702722-21Isolated09:38:542
9109889944619,29cyclictest0-21swapper/823:48:5914
9109959944112,429cyclictest0-21swapper/1523:27:457
9109959944011,30cyclictest0-21swapper/1500:39:217
910995994399,429cyclictest0-21swapper/1500:34:537
910995994389,428cyclictest0-21swapper/1523:23:287
9109799942326,395cyclictest0-21swapper/223:47:448
91098399408407,1cyclictest0-21swapper/323:47:569
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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