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2025-07-10 - 18:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Thu Jul 10, 2025 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10253629943911,28cyclictest0-21swapper/1400:27:596
10253249943023,406cyclictest0-21swapper/400:12:4610
10253249942621,405cyclictest0-21swapper/423:48:2510
1025313994179,407cyclictest0-21swapper/100:14:491
1025313994147,407cyclictest0-21swapper/123:49:281
10253139941410,404cyclictest0-21swapper/123:41:251
1025362994120,411cyclictest0-21swapper/1419:52:126
102534399412412,0cyclictest0-21swapper/923:35:0015
1025358994114,404cyclictest3411944-21x0vncserver00:26:175
102534399411411,0cyclictest0-21swapper/923:42:5815
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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