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2025-03-16 - 22:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Sun Mar 16, 2025 00:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
229177799520336,65cyclictest2270857-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
19:25:040
229177799520336,65cyclictest2270857-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
19:25:030
229177799520336,65cyclictest2217997-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
19:23:160
229177799517336,64cyclictest2270857-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
19:34:020
229177799463335,68cyclictest2577570-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
21:14:140
22918309943812,0cyclictest0-21swapper/1519:28:037
22918309943812,0cyclictest0-21swapper/1519:28:027
229180699418418,0cyclictest0-21swapper/819:34:0214
229180699418418,0cyclictest0-21swapper/819:25:0314
229180699418418,0cyclictest0-21swapper/819:25:0314
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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