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2024-09-08 - 10:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Sun Sep 08, 2024 00:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35222679948526,58cyclictest0-21swapper/022:11:590
35222679948224,28cyclictest0-21swapper/021:26:590
352227199480416,1cyclictest3765598-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
20:36:591
35223049947523,58cyclictest0-21swapper/1021:08:592
352228299472408,1cyclictest3485307-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
19:26:4510
352227199471407,1cyclictest3674531-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
20:33:581
35222809946910,58cyclictest0-21swapper/322:26:599
35222829946813,58cyclictest0-21swapper/400:02:4410
352228299467403,1cyclictest3855852-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
22:03:2010
35222829946611,58cyclictest0-21swapper/421:32:1410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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