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2025-03-18 - 04:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot7.osadl.org (updated Tue Mar 18, 2025 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
108024299485422,1cyclictest1295483-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
21:45:434
108024699477415,1cyclictest807731-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
19:31:055
108021099477410,2cyclictest1295483-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
21:08:128
108024699462400,1cyclictest807731-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
20:06:475
108024699461399,1cyclictest1181351-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
20:00:395
108022499450387,1cyclictest1621188-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
21:52:2312
108022499450387,1cyclictest1621188-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
21:52:2312
108023699431369,1cyclictest1563410-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
21:46:532
108022499429367,1cyclictest1621188-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
21:47:3312
108023699425360,2cyclictest1507150-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
21:34:542
108020299416406,9cyclictest0-21swapper/000:25:120
108020299414293,62cyclictest1736444-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
22:55:230
108020299413292,62cyclictest1507150-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
21:45:100
108023099408407,1cyclictest0-21swapper/821:52:2314
108023099408407,1cyclictest0-21swapper/821:52:2314
1080217994020,1cyclictest0-21swapper/421:45:4310
108021099402401,1cyclictest0-21swapper/221:46:548
108021099394393,1cyclictest0-21swapper/221:34:548
108023099393392,1cyclictest819-21md2_raid121:08:1114
108023699377377,0cyclictest0-21swapper/1021:08:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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