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2024-09-12 - 23:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot7.osadl.org (updated Thu Sep 12, 2024 00:45:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12999439944425,419cyclictest0-21swapper/1400:06:346
129992599438416,15cyclictest2286394-21kworker/0:2+events@
igb_watchdog_task
12:54:560
129992599438416,15cyclictest2286394-21kworker/0:2+events@
igb_watchdog_task
03:04:450
129992899437415,19cyclictest0-21swapper/300:35:369
129993399424423,1cyclictest2470670-21kthreadcore00:20:2214
129993399424423,1cyclictest2470670-21kthreadcore00:20:2114
129993699422422,0cyclictest27350irq/129-xhci_hcd19:43:233
129992599422404,13cyclictest2286394-21kworker/0:2+events@
igb_watchdog_task
09:06:100
129993199421418,1cyclictest2009569-21python300:35:3612
12999389941920,30cyclictest0-21swapper/1300:00:205
129993499416347,2cyclictest2268073-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
00:29:0015
1299943994150,414cyclictest0-21swapper/1400:28:466
1299928994140,2cyclictest0-21swapper/300:14:329
1299935994136,403cyclictest952420pipewire-pulse00:20:142
1299935994136,403cyclictest952420pipewire-pulse00:20:142
129993299413340,2cyclictest2341559-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
23:58:2113
129993399412412,0cyclictest0-21swapper/823:57:2114
1299928994109,399cyclictest0-21swapper/300:29:449
129992599410348,2cyclictest2268073-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
00:35:550
12999439940920,388cyclictest0-21swapper/1423:53:206
129993799407406,1cyclictest0-21swapper/1200:00:444
1299928994076,401cyclictest0-21swapper/323:54:439
129994399406400,2cyclictest0-21swapper/1400:35:376
1299928994066,398cyclictest0-21swapper/300:04:439
129993499404339,1cyclictest1434715-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
19:43:2215
129993699402399,2cyclictest2248386-21kworker/11:0+events@
output_poll_execute
00:29:453
1299935994024,397cyclictest2439330-21MediaTimer2
129993599401399,1cyclictest1638508-21kworker/10:0+events@
output_poll_execute
23:56:432
1299943994000,400cyclictest0-21swapper/1400:31:436
1299943994000,400cyclictest0-21swapper/1400:14:326
129993699398395,2cyclictest2248386-21kworker/11:0+events@
output_poll_execute
23:54:443
129993699398395,2cyclictest2248386-21kworker/11:0+events@
output_poll_execute
00:04:443
129993699398376,2cyclictest0-21swapper/1100:35:373
129992799398395,3cyclictest712112-21Renderer00:20:158
129992799398395,3cyclictest712112-21Renderer00:20:148
129993699397396,1cyclictest27350irq/129-xhci_hcd00:09:443
1299936993970,396cyclictest0-21swapper/1123:59:503
129993699396393,2cyclictest2343295-21kworker/11:2+events@
output_poll_execute
00:13:453
1299945993950,394cyclictest0-21swapper/1523:58:227
129993599395394,1cyclictest0-21swapper/1000:35:472
129993499395393,2cyclictest0-21swapper/900:09:2015
1299943993940,394cyclictest0-21swapper/1423:56:216
129993599394393,1cyclictest0-21swapper/1000:16:452
129993599394393,1cyclictest0-21swapper/1000:16:442
129993199394392,1cyclictest2416438-21kworker/6:2+events@
output_poll_execute
00:14:4312
129992899392390,2cyclictest8991-21Xorg00:23:519
129992899392390,2cyclictest8991-21Xorg00:23:509
129994599390389,1cyclictest0-21swapper/1500:35:557
1299926993903,386cyclictest0-21swapper/100:04:211
129992999389388,1cyclictest25850irq/128-ahci[0000:00:17.0]00:20:2210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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