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2024-04-24 - 00:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot7.osadl.org (updated Tue Apr 23, 2024 00:45:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9018262207156,42sleep150-21swapper/1519:07:377
9019312201181,10sleep120-21swapper/1219:08:234
9017552199159,10sleep60-21swapper/619:06:4112
9020412182167,8sleep80-21swapper/819:09:3914
9017252181162,9sleep50-21swapper/519:06:2411
9019552180160,10sleep130-21swapper/1319:08:405
9019262175156,10sleep70-21swapper/719:08:1813
9017782175155,10sleep110-21swapper/1119:07:023
9017532169149,10sleep40-21swapper/419:06:3910
9020612168149,11sleep30-21swapper/319:09:509
9019282132112,10sleep90-21swapper/919:08:1915
9019072129112,9sleep100-21swapper/1019:08:052
9018112113110,1sleep10-21swapper/119:07:241
901914210340,53sleep140-21swapper/1419:08:086
1976920870,75pipewire-pulse0-21swapper/019:08:150
90200726450,6sleep20-21swapper/219:09:168
90291099550,25cyclictest0-21swapper/1522:45:247
35238882540,0sleep120-21swapper/1222:10:274
90291099520,24cyclictest0-21swapper/1500:10:277
902905995251,1cyclictest1558413-1kworker/u33:220:30:182
90291099500,21cyclictest0-21swapper/1519:50:247
12230862480,0sleep40-21swapper/400:20:0310
90291099450,15cyclictest0-21swapper/1500:28:407
90291099440,15cyclictest0-21swapper/1500:05:407
90291099440,14cyclictest0-21swapper/1523:56:457
902897994428,0cyclictest0-21swapper/221:16:508
902896994420,13cyclictest0-21swapper/100:07:181
90291099430,13cyclictest0-21swapper/1500:23:417
90291099400,19cyclictest0-21swapper/1522:21:047
90290799400,15cyclictest0-21swapper/1221:10:224
143999400,0ntpd109-21ksoftirqd/1321:29:015
90289699393,11cyclictest0-21swapper/123:45:201
90291099380,9cyclictest0-21swapper/1523:30:237
90291099380,8cyclictest0-21swapper/1500:37:267
90291099370,8cyclictest0-21swapper/1522:08:457
90291099370,8cyclictest0-21swapper/1519:28:267
902901993712,0cyclictest1983014-21kworker/u32:420:45:4612
902898993636,0cyclictest11983-21InputThread20:46:409
902895993636,0cyclictest0-21swapper/021:41:400
143999360,0ntpd0-21swapper/1322:29:405
902896993423,11cyclictest141rcu_preempt23:01:241
90289699338,0cyclictest0-21swapper/122:17:271
902896993320,13cyclictest0-21swapper/123:12:231
902909993231,1cyclictest0-21swapper/1421:51:586
902905993232,0cyclictest11983-21InputThread20:22:002
902896993219,13cyclictest0-21swapper/122:06:291
902909993131,0cyclictest0-21swapper/1419:57:426
90290199316,25cyclictest3233597-21kworker/u32:321:51:3512
90291099300,2cyclictest0-21swapper/1523:02:107
90291099300,1cyclictest0-21swapper/1522:33:417
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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