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2021-01-21 - 05:04

Intel(R) Core(TM) i9-9900K CPU @ 3.60GHz, Linux 5.10.8-rt24 (Profile)

Latency plot of system in rack #0, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot7.osadl.org (updated Thu Jan 21, 2021 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
77794399419419,0cyclictest0-21swapper/1000:03:512
7774962415410,3sleep90-21swapper/919:09:2015
7774962415410,3sleep90-21swapper/919:09:2015
7769702415409,3sleep80-21swapper/819:05:0314
7769702415409,3sleep80-21swapper/819:05:0314
7770472413408,2sleep20-21swapper/219:05:458
7770472413408,2sleep20-21swapper/219:05:458
77795199409409,0cyclictest0-21swapper/1200:22:244
7770932408403,3sleep70-21swapper/719:06:0613
7770932408403,3sleep70-21swapper/719:06:0613
7770462405400,3sleep10-21swapper/119:05:441
7770462405400,3sleep10-21swapper/119:05:441
7770142405399,3sleep60-21swapper/619:05:3312
7770142405399,3sleep60-21swapper/619:05:3312
77791999403402,1cyclictest1197685-21kworker/u32:000:22:2510
7774162403399,2sleep140-21swapper/1419:08:376
7774162403399,2sleep140-21swapper/1419:08:376
7775372401395,3sleep30-21swapper/319:09:469
7775372401395,3sleep30-21swapper/319:09:469
7769772401395,3sleep130-21swapper/1319:05:085
7769772401395,3sleep130-21swapper/1319:05:085
7769762401396,3sleep120-21swapper/1219:05:074
7769762401396,3sleep120-21swapper/1219:05:074
7774622400395,3sleep00-21swapper/019:08:550
7774622400395,3sleep00-21swapper/019:08:550
7772382400395,3sleep150-21swapper/1519:07:187
7772382400395,3sleep150-21swapper/1519:07:187
7772492399394,3sleep40-21swapper/419:07:2310
7772492399394,3sleep40-21swapper/419:07:2310
77793299398398,0cyclictest0-21swapper/720:23:4913
7770902395390,3sleep50-21swapper/519:06:0411
7770902395390,3sleep50-21swapper/519:06:0411
7771012393388,3sleep110-21swapper/1119:06:103
7771012393388,3sleep110-21swapper/1119:06:103
77790499388388,0cyclictest0-21swapper/000:31:330
77792499387386,1cyclictest819554-21kworker/u32:220:05:4111
77791599387387,0cyclictest1218-21snmpd20:05:419
77796299382382,0cyclictest1218-21snmpd00:22:257
77792799379379,0cyclictest18450irq/126-ahci[0000:03:5112
77791399375374,1cyclictest1116984-21kworker/u32:300:31:328
7770972375369,3sleep100-21swapper/1019:06:092
7770972375369,3sleep100-21swapper/1019:06:092
77794399374373,1cyclictest813902-21kworker/u32:120:23:492
77793699355355,0cyclictest1218-21snmpd00:31:3314
77794699346346,0cyclictest0-21swapper/1120:05:423
77791599343342,1cyclictest832443-21kworker/u32:520:10:109
77796299335334,0cyclictest318934-21Web00:50:347
77791399334333,1cyclictest1138681-21kworker/u32:400:03:528
77796299333333,0cyclictest0-21swapper/1522:42:217
77793899331331,0cyclictest0-21swapper/921:27:2815
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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