You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2022-01-23 - 18:39

Intel(R) Core(TM) i9-9900K CPU @ 3.60GHz, Linux 5.15.13-rt26 (Profile)

Latency plot of system in rack #0, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Sun Jan 23, 2022 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4062523994474,443cyclictest4188545-21kworker/15:109:29:177
4062523994474,443cyclictest4071877-21kworker/15:008:13:077
4062523994474,443cyclictest4071877-21kworker/15:008:13:067
406252399446445,1cyclictest4164114-21kworker/15:009:00:517
406252399444443,1cyclictest4071877-21kworker/15:007:59:437
406252399444443,1cyclictest4071877-21kworker/15:007:46:067
406252399443442,1cyclictest4071877-21kworker/15:008:18:187
4062523994420,2cyclictest4071877-21kworker/15:007:19:087
406251299440439,1cyclictest4132167-21kworker/7:009:29:1613
406251299440439,1cyclictest309137-21kworker/7:208:13:0713
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional