You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-16 - 00:21
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot8.osadl.org (updated Tue Jul 15, 2025 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12891099426424,1cyclictest28550irq/127-xhci_hcd12:35:4814
12891099426424,1cyclictest28550irq/127-xhci_hcd12:06:4914
12891099426424,1cyclictest28550irq/127-xhci_hcd12:06:4914
12891099426424,1cyclictest28550irq/127-xhci_hcd09:52:2914
12891099425424,1cyclictest28550irq/127-xhci_hcd09:26:0514
12891099425424,1cyclictest28550irq/127-xhci_hcd07:25:3714
12891099425423,1cyclictest28550irq/127-xhci_hcd11:34:2114
12891099425423,1cyclictest28550irq/127-xhci_hcd11:28:0514
12890899423419,3cyclictest342486-21kworker/u64:4+events_unbound12:30:3612
12891099422420,1cyclictest28550irq/127-xhci_hcd09:01:4314
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional