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2022-11-29 - 19:44

x86 Intel Core i9-9900K @3600 MHz, Linux 5.15.49-rt47 (Profile)

Latency plot of system in rack #0, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100, highest latencies:
System rack0slot8.osadl.org (updated Tue Nov 29, 2022 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
350194599425423,2cyclictest3677769-21turbostat09:44:554
350192699425421,4cyclictest2507340-21kworker/0:008:02:560
350194199424423,1cyclictest3552995-21turbostat08:09:563
350192999424423,1cyclictest26750irq/127-xhci_hc08:02:568
350194899422421,1cyclictest0-21swapper/1509:49:597
350192699421417,4cyclictest3884196-21kworker/0:211:27:500
350192699421416,5cyclictest2507340-21kworker/0:007:25:570
350192699421416,5cyclictest2507340-21kworker/0:007:25:570
350192999420419,1cyclictest26750irq/127-xhci_hc11:27:508
350192699420415,5cyclictest3597964-21kworker/0:209:04:440
350192999419418,1cyclictest26750irq/127-xhci_hc09:04:448
350192999419418,1cyclictest26750irq/127-xhci_hc07:25:578
350192999419418,1cyclictest26750irq/127-xhci_hc07:25:578
350192999418416,2cyclictest26750irq/127-xhci_hc07:23:388
350192999418416,2cyclictest26750irq/127-xhci_hc07:23:388
350192699418414,4cyclictest2507340-21kworker/0:007:23:380
350192699418414,4cyclictest2507340-21kworker/0:007:23:380
3501948994140,414cyclictest0-21swapper/1512:25:007
3501948994130,413cyclictest0-21swapper/1511:00:007
350193899413411,2cyclictest0-21swapper/907:41:5915
3501948994100,409cyclictest0-21swapper/1511:45:007
350194699410409,1cyclictest0-21swapper/1308:17:595
350193399410409,1cyclictest3608177-21turbostat09:09:5510
350194699408407,1cyclictest0-21swapper/1308:04:565
3501948994060,406cyclictest0-21swapper/1510:50:017
350194099406404,2cyclictest3505974-21kworker/u32:207:19:182
350194799404404,0cyclictest0-21swapper/1411:12:586
350194799404404,0cyclictest0-21swapper/1409:32:596
3501948994030,403cyclictest0-21swapper/1509:30:007
3501948994010,401cyclictest0-21swapper/1508:00:007
350194099401400,1cyclictest0-21swapper/1007:44:562
3501948993990,398cyclictest0-21swapper/1510:45:017
350193899399397,2cyclictest3656156-21turbostat09:34:5515
350193599399396,1cyclictest3673447-21kworker/6:009:37:5812
350194699398392,6cyclictest4367-21gnome-shell07:19:185
350192899398396,2cyclictest0-21swapper/112:14:551
3501948993950,395cyclictest0-21swapper/1512:20:007
3501948993950,395cyclictest0-21swapper/1510:55:007
350194599395395,0cyclictest0-21swapper/1209:09:544
3501948993940,394cyclictest0-21swapper/1509:05:007
350194199394394,0cyclictest3999967-21turbostat12:19:543
350193799394389,2cyclictest0-21swapper/807:41:5914
350193699394392,2cyclictest0-21swapper/711:59:5513
350193499394394,0cyclictest0-21swapper/507:31:1611
3501948993930,393cyclictest0-21swapper/1512:40:007
3501948993930,393cyclictest0-21swapper/1509:40:007
3501948993920,392cyclictest0-21swapper/1511:54:597
350194699392391,1cyclictest0-21swapper/1310:06:245
350193699392391,1cyclictest3710111-21turbostat09:55:0013
3501948993910,391cyclictest0-21swapper/1510:15:007
350194799391390,1cyclictest0-21swapper/1411:47:516
350194799391390,1cyclictest0-21swapper/1410:06:506
350194799391390,0cyclictest0-21swapper/1410:33:516
350194699391389,2cyclictest0-21swapper/1309:19:555
3501948993900,390cyclictest0-21swapper/1510:20:007
3501948993900,390cyclictest0-21swapper/1510:20:007
3501948993900,390cyclictest0-21swapper/1510:10:007
3501948993900,390cyclictest0-21swapper/1509:20:007
350194799390390,0cyclictest0-21swapper/1412:33:236
350194799390390,0cyclictest0-21swapper/1412:17:116
350194799390390,0cyclictest0-21swapper/1411:05:596
350194799390390,0cyclictest0-21swapper/1410:44:496
350194799390390,0cyclictest0-21swapper/1410:18:356
350194799390390,0cyclictest0-21swapper/1410:18:356
350194799390390,0cyclictest0-21swapper/1409:58:516
350194799390390,0cyclictest0-21swapper/1409:52:016
350194799390390,0cyclictest0-21swapper/1409:41:376
350194799390390,0cyclictest0-21swapper/1409:39:326
350194799390390,0cyclictest0-21swapper/1408:22:536
350194799390390,0cyclictest0-21swapper/1407:55:296
350194799390390,0cyclictest0-21swapper/1407:47:456
350194799390390,0cyclictest0-21swapper/1407:42:496
350194799390389,1cyclictest0-21swapper/1411:29:126
350194799390389,0cyclictest0-21swapper/1411:36:406
350194799390388,1cyclictest0-21swapper/1410:48:186
350194799389389,0cyclictest0-21swapper/1412:37:466
350194799389389,0cyclictest0-21swapper/1412:25:026
350194799389389,0cyclictest0-21swapper/1412:20:356
350194799389389,0cyclictest0-21swapper/1412:08:306
350194799389389,0cyclictest0-21swapper/1411:55:266
350194799389389,0cyclictest0-21swapper/1411:50:266
350194799389389,0cyclictest0-21swapper/1411:41:096
350194799389389,0cyclictest0-21swapper/1411:20:136
350194799389389,0cyclictest0-21swapper/1411:18:526
350194799389389,0cyclictest0-21swapper/1410:56:376
350194799389389,0cyclictest0-21swapper/1410:50:256
350194799389389,0cyclictest0-21swapper/1410:12:266
350194799389389,0cyclictest0-21swapper/1409:25:146
350194799389389,0cyclictest0-21swapper/1408:52:136
350194799389389,0cyclictest0-21swapper/1408:49:446
350194799389389,0cyclictest0-21swapper/1408:40:096
350194799389389,0cyclictest0-21swapper/1408:32:186
350194799389389,0cyclictest0-21swapper/1407:53:126
350194799389389,0cyclictest0-21swapper/1407:31:056
350194799389389,0cyclictest0-21swapper/1407:28:326
350194799389389,0cyclictest0-21swapper/1407:28:326
350194799389389,0cyclictest0-21swapper/1407:24:306
350194799389389,0cyclictest0-21swapper/1407:24:306
350194799389389,0cyclictest0-21swapper/1407:18:246
350194799389389,0cyclictest0-21swapper/1407:10:326
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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