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2024-09-20 - 18:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot8.osadl.org (updated Fri Sep 20, 2024 12:46:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
215495699790,78cyclictest2276576-21meminfo11
215496499700,69cyclictest2412015-21meminfo5
215496199690,68cyclictest2363864-21meminfo2
215496499680,67cyclictest2337671-21meminfo5
215496399680,67cyclictest2416249-21meminfo4
215495699680,67cyclictest2237116-21meminfo11
215495699680,67cyclictest2237116-21meminfo11
215495699650,64cyclictest2215156-21meminfo11
215495199650,65cyclictest2402722-21meminfo0
215496299640,63cyclictest2398502-21meminfo3
215496199640,63cyclictest2341893-21meminfo2
215495899640,63cyclictest2359633-21meminfo13
215496499630,62cyclictest2315711-21meminfo5
215496499630,62cyclictest2237117-21meminfo5
215496499630,62cyclictest2237117-21meminfo5
215496299630,62cyclictest2307228-21meminfo3
215496299630,62cyclictest2219382-21meminfo3
215496299630,62cyclictest2197980-21meminfo3
215496299630,62cyclictest2171797-21meminfo3
215496199630,62cyclictest2355137-21meminfo2
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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