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2024-04-24 - 03:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot8.osadl.org (updated Tue Apr 23, 2024 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
148377299487401,2cyclictest1560386-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
08:43:3215
148376899475402,1cyclictest1729684-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
12:31:3611
148376899473399,2cyclictest1549219-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
08:26:5011
148376899472400,1cyclictest1769935-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
12:28:0011
148376399470399,4cyclictest1502412-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
08:19:530
148377299468393,2cyclictest1587327-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
09:10:3215
148377099464389,2cyclictest1618250-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
10:01:2013
148376499464388,2cyclictest1576768-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
09:15:211
148376699461389,2cyclictest1687359-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
11:36:089
148377099459386,1cyclictest1751264-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
12:06:1613
148377099457385,1cyclictest1502412-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
08:20:5513
148377799454381,2cyclictest1778884-21kworker/u64:6+events_unbound@
intel_display_power_put_async_work
12:38:225
148377799450377,1cyclictest1502412-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
08:37:385
148377299450376,2cyclictest1560386-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
09:02:2315
14837719945015,434cyclictest0-21swapper/807:14:0614
148377799448375,1cyclictest1741570-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
12:13:035
148377299448376,1cyclictest1613848-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
10:17:2915
1483771994421,17cyclictest0-21swapper/812:38:2314
148376499439366,1cyclictest1729684-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
12:37:501
148377999436436,0cyclictest0-21swapper/1507:10:237
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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