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2024-12-11 - 13:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Tue Dec 10, 2024 12:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
85342499940,93cyclictest967202-21meminfo09:05:209
85342499860,85cyclictest1004721-21meminfo09:50:159
85342299860,85cyclictest866439-21meminfo07:20:231
85343199830,82cyclictest1054300-21meminfo10:40:2114
85343199830,82cyclictest1054300-21meminfo10:40:2014
85342499790,78cyclictest1108642-21meminfo11:35:209
85342299790,78cyclictest1063887-21meminfo10:50:261
85342699780,77cyclictest1010098-21meminfo09:55:2110
85343699760,75cyclictest976788-21meminfo09:15:225
85342499760,75cyclictest1147761-21meminfo12:15:239
85343599750,74cyclictest947208-21meminfo08:45:234
85342399750,74cyclictest1093452-21meminfo11:20:258
85343199740,73cyclictest1083892-21meminfo11:10:2514
85342799740,73cyclictest1133382-21meminfo12:00:2111
85343199730,72cyclictest957343-21meminfo08:55:2014
85343099730,72cyclictest891200-21meminfo07:45:1913
85342299730,72cyclictest891201-21meminfo07:45:191
85342199730,72cyclictest1049529-21meminfo10:35:220
85342199730,72cyclictest1039674-21meminfo10:25:190
85343399720,72cyclictest881659-21meminfo07:35:262
85342699720,71cyclictest942424-21meminfo08:40:1910
85343699710,70cyclictest908021-21meminfo08:05:205
85343199710,70cyclictest1034303-21meminfo10:20:1914
85342499710,70cyclictest903197-21meminfo08:00:169
85342299710,70cyclictest1044759-21meminfo10:30:261
85343199700,69cyclictest1004722-21meminfo09:50:1514
85342499700,69cyclictest1162961-21meminfo12:30:199
85342299700,69cyclictest1059103-21meminfo10:45:221
85342199700,69cyclictest947207-21meminfo08:45:220
85343599690,68cyclictest1103865-21meminfo11:30:214
85343599690,68cyclictest1054306-21meminfo10:40:214
85343599690,68cyclictest1054306-21meminfo10:40:214
85343599690,68cyclictest1015141-21meminfo10:00:194
85343399690,68cyclictest908022-21meminfo08:05:212
85343399690,68cyclictest1108644-21meminfo11:35:202
85342299690,68cyclictest886422-21meminfo07:40:201
85342299690,68cyclictest1142988-21meminfo12:10:251
85343399680,67cyclictest1010100-21meminfo09:55:222
85342499680,67cyclictest981562-21meminfo09:20:199
85342499680,67cyclictest1049530-21meminfo10:35:229
85342399680,67cyclictest942425-21meminfo08:40:218
85342299680,67cyclictest988789-21meminfo09:30:151
85342299680,67cyclictest912826-21meminfo08:10:211
85342299680,67cyclictest1088673-21meminfo11:15:261
85342199680,67cyclictest876862-21meminfo07:30:220
85342199680,67cyclictest1138188-21meminfo12:05:190
85342199680,67cyclictest1128329-21meminfo11:55:230
85343699670,66cyclictest861660-21meminfo07:15:215
85343699670,66cyclictest1152560-21meminfo12:20:225
85343599670,66cyclictest1167761-21meminfo12:35:214
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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