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2022-06-27 - 16:02

x86 Intel Core i9-9900K @3600 MHz, Linux 5.15.49-rt47 (Profile)

Latency plot of system in rack #0, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Mon Jun 27, 2022 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117137994440,5cyclictest6871-21chrome11:42:2413
1171379944011,0cyclictest0-21swapper/710:09:0413
11714699434433,1cyclictest106340-21kworker/13:109:11:205
117142994280,1cyclictest331379-21ThreadPoolForeg09:58:493
117139994280,0cyclictest0-21swapper/809:22:1014
117148994270,1cyclictest115623-21ThreadPoolForeg11:54:167
11713799427423,3cyclictest530823-21turbostat11:40:0013
117145994260,426cyclictest0-21swapper/1208:32:234
11714299426425,1cyclictest237150-21kworker/u32:409:23:343
11714299426425,1cyclictest111263-21kworker/u32:207:54:363
11713999425422,2cyclictest0-21swapper/812:08:3114
117148994240,424cyclictest0-21swapper/1507:58:017
11714299424423,1cyclictest322296-21kworker/u32:411:28:313
117139994240,424cyclictest0-21swapper/807:46:2214
117139994220,422cyclictest0-21swapper/810:05:1114
11713299422420,2cyclictest570343-21turbostat12:04:558
11714899421419,1cyclictest0-21swapper/1511:19:127
11714299421419,2cyclictest75723-21kworker/u32:010:06:513
11713799421420,1cyclictest151533-21turbostat07:45:0013
11713799421419,2cyclictest342667-21turbostat10:05:0013
11714899420419,1cyclictest0-21swapper/1508:13:577
11714299420420,0cyclictest0-21swapper/1108:14:413
11714099419417,2cyclictest0-21swapper/908:59:5515
11713499419418,1cyclictest26650irq/127-xhci_hc09:22:1010
11713999418417,1cyclictest0-21swapper/811:11:0114
11713799418418,0cyclictest0-21swapper/709:09:1013
11712799418417,1cyclictest333076-21turbostat10:04:550
11713799417417,0cyclictest0-21swapper/710:52:3213
11714899416414,2cyclictest0-21swapper/1510:35:007
11714899415413,2cyclictest0-21swapper/1508:05:007
11713499414413,1cyclictest26650irq/127-xhci_hc08:49:5810
11713499414413,1cyclictest26650irq/127-xhci_hc08:49:5810
11713499413412,1cyclictest26650irq/127-xhci_hc12:08:3110
11713499413412,1cyclictest26650irq/127-xhci_hc07:46:2210
11713799411409,2cyclictest206201-21turbostat08:45:0013
11713799409408,1cyclictest271576-21turbostat09:30:0113
11714899408407,1cyclictest0-21swapper/1512:30:007
11713599408404,1cyclictest75723-21kworker/u32:008:46:4911
11713599408404,1cyclictest75723-21kworker/u32:008:46:4911
11712799408408,0cyclictest0-21swapper/010:52:320
11714899407407,0cyclictest0-21swapper/1508:10:007
11713999407407,0cyclictest0-21swapper/810:19:5514
11713799407406,1cyclictest240167-21turbostat09:15:0013
11713499407406,1cyclictest26650irq/127-xhci_hc11:11:0110
11713399406405,1cyclictest1420-21snmpd11:42:589
11713499405404,1cyclictest75723-21kworker/u32:009:11:2010
11713499405403,2cyclictest240167-21turbostat09:19:5510
11713399405402,2cyclictest307738-21kworker/u32:309:58:499
11713599404404,0cyclictest0-21swapper/512:19:4211
11713599404404,0cyclictest0-21swapper/510:13:4211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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