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2025-06-12 - 22:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Thu Jun 12, 2025 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
585198993160,314cyclictest732303-21meminfo09:45:208
585209991200,119cyclictest876381-21meminfo12:20:215
585205991170,115cyclictest788397-21meminfo10:45:2015
585197991140,113cyclictest798039-21meminfo10:55:211
58520699920,91cyclictest816216-21meminfo11:15:212
58520099880,87cyclictest607615-21meminfo07:30:2010
58519999870,86cyclictest736750-21meminfo09:50:209
58520399860,85cyclictest862886-21meminfo12:05:1913
58520899840,84cyclictest667697-21meminfo08:35:214
58520699840,83cyclictest858396-21meminfo12:00:212
58520799830,81cyclictest746821-21meminfo10:00:193
58520999820,81cyclictest672161-21meminfo08:40:175
58520699770,76cyclictest714135-21meminfo09:25:212
58520699770,76cyclictest616547-21meminfo07:40:182
58519799760,75cyclictest751309-21meminfo10:05:211
58519599750,73cyclictest590845-21meminfo07:15:020
58520599740,73cyclictest704488-21meminfo09:15:2115
58519999730,72cyclictest718832-21meminfo09:30:219
58520999720,71cyclictest602903-21meminfo07:25:215
58519799720,71cyclictest858394-21meminfo12:00:211
58520899710,70cyclictest876383-21meminfo12:20:214
58520799710,70cyclictest830559-21meminfo11:30:213
58520799710,70cyclictest830559-21meminfo11:30:213
58520699710,70cyclictest802748-21meminfo11:00:222
58520699710,70cyclictest691050-21meminfo09:00:252
58520499700,69cyclictest723296-21meminfo09:35:2214
58520199700,69cyclictest648892-21meminfo08:15:2011
58520099700,69cyclictest881557-21meminfo12:25:2710
58519999700,69cyclictest746819-21meminfo10:00:199
58519599700,68cyclictest639918-21meminfo08:05:210
58520799690,68cyclictest621112-21meminfo07:45:203
58520699690,68cyclictest890714-21meminfo12:35:202
58520199690,68cyclictest635432-21meminfo08:00:2111
58520999680,67cyclictest890715-21meminfo12:35:205
58520199680,67cyclictest699989-21meminfo09:10:2011
58520199680,67cyclictest699989-21meminfo09:10:2011
58520199680,67cyclictest644389-21meminfo08:10:2211
58520099680,67cyclictest871887-21meminfo12:15:2310
58520099680,67cyclictest848526-21meminfo11:50:2210
58519999680,67cyclictest676725-21meminfo08:45:219
58519599680,67cyclictest760410-21meminfo10:15:200
58520699670,66cyclictest839481-21meminfo11:40:202
58520499670,67cyclictest825856-21meminfo11:25:2114
58520499670,67cyclictest825856-21meminfo11:25:2114
58520199670,66cyclictest667699-21meminfo08:35:2111
58520099670,66cyclictest867368-21meminfo12:10:1910
58520099670,66cyclictest764967-21meminfo10:20:2010
58519999670,66cyclictest695527-21meminfo09:05:219
58519799670,66cyclictest770160-21meminfo10:25:201
58519799670,66cyclictest681190-21meminfo08:50:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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