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2024-04-26 - 08:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Thu Apr 25, 2024 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
351147499576372,71cyclictest3560969-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
08:16:080
351147499572368,71cyclictest3760500-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
12:13:420
351147499571367,71cyclictest3626191-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
09:26:070
351147499569365,71cyclictest3463564-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
08:00:540
351148499520424,3cyclictest3520606-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
07:53:512
351147499508370,71cyclictest3778661-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
12:29:000
351148299502423,3cyclictest3663105-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
10:25:2214
351147899495420,2cyclictest3626191-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
09:20:1210
351148099494420,1cyclictest3542873-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
09:00:0112
351148099494420,1cyclictest3542873-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
09:00:0112
351147899494421,1cyclictest3542873-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
08:50:0810
351148099493421,1cyclictest3644509-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
10:41:0012
351148099493418,2cyclictest3685982-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
11:34:1812
351148499492419,1cyclictest3542873-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
09:14:142
351148099489417,1cyclictest3663105-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
10:36:0412
351148099489417,1cyclictest3644509-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
11:10:0212
351148099489417,1cyclictest3560969-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
08:04:2512
351148099487415,1cyclictest3761462-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
11:58:4212
351148099487415,1cyclictest3761462-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
11:58:4212
351148099487415,1cyclictest3561264-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
08:31:2712
351148099487414,1cyclictest3542873-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
08:05:3512
351148099486412,2cyclictest3644509-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
11:47:0612
351148099486412,2cyclictest3644509-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
11:47:0612
351147699482409,1cyclictest3520606-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
09:05:518
351147699482409,1cyclictest3520606-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
09:05:508
351148699476403,1cyclictest3520606-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
07:23:534
351148699473401,1cyclictest3619596-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
09:30:494
351148699466394,1cyclictest3774344-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
12:23:364
351147999465392,1cyclictest3619596-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
10:27:2111
351147999461388,1cyclictest3644509-21kworker/u64:5+events_unbound@
intel_display_power_put_async_work
10:18:3711
351148299460387,1cyclictest3605129-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
08:56:1414
351148299460387,1cyclictest3605129-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
08:56:1414
351148299459387,1cyclictest3760500-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
12:17:3614
351147799445374,1cyclictest3502397-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
07:53:539
351148299437437,0cyclictest0-21swapper/810:34:4414
3511484994340,433cyclictest0-21swapper/1011:32:272
351147899433431,1cyclictest0-21swapper/409:00:0210
351147899433431,1cyclictest0-21swapper/409:00:0110
351148999430428,1cyclictest0-21swapper/1409:00:016
351148999430428,1cyclictest0-21swapper/1409:00:016
351147699429428,1cyclictest1758-21snmpd11:32:278
351147499427397,22cyclictest1281366-21kworker/0:0+events@
igb_watchdog_task
07:09:020
351148499426424,1cyclictest0-21swapper/1009:00:012
351148499426424,1cyclictest0-21swapper/1009:00:012
351147499426411,9cyclictest1281366-21kworker/0:0+events@
igb_watchdog_task
08:47:510
3511478994240,423cyclictest0-21swapper/407:23:5310
351148999423423,0cyclictest0-21swapper/1410:41:006
351148299423422,1cyclictest0-21swapper/807:29:2614
351148999422422,0cyclictest0-21swapper/1407:53:516
351147899422421,0cyclictest0-21swapper/409:30:4910
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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