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2025-11-17 - 07:01
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Note that this system runs a non-RT kernel.
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Sat Nov 15, 2025 12:45:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25548729910700,1069cyclictest2793968-21modprobe11:11:1115
2554875997060,703cyclictest2719298-21meminfo09:55:234
2554875994900,484cyclictest2877896-21meminfo12:35:264
2554862994860,485cyclictest2763116-21meminfo10:40:241
2554861994740,472cyclictest2868220-21meminfo12:25:220
2554861994610,459cyclictest2842687-21meminfo12:00:230
2554866993500,348cyclictest2772682-21meminfo10:50:2311
2554866993500,348cyclictest2772682-21meminfo10:50:2211
2554875993400,338cyclictest2763117-21meminfo10:40:244
2554866993100,308cyclictest2758297-21meminfo10:35:2311
2554874992920,291cyclictest2873112-21meminfo12:30:243
2554861992670,265cyclictest2802779-21meminfo11:20:200
2554871992210,219cyclictest2788044-21meminfo11:05:2214
2554862992130,211cyclictest2748608-21meminfo10:25:231
2554875991661,163cyclictest2758298-21meminfo10:35:224
2554866991560,155cyclictest2724335-21meminfo10:00:2411
25548779914317,35cyclictest0-21swapper/1411:46:326
25548669914288,28cyclictest2799340-21winedevice.exe11:16:5911
2554875991280,127cyclictest2665015-21meminfo09:00:244
2554863991220,121cyclictest2788041-21meminfo11:05:218
25548789911952,64cyclictest0-21swapper/1511:16:287
2554876991150,112cyclictest2792691-21meminfo11:10:235
2554872991150,114cyclictest2743213-21meminfo10:20:2315
255487899107106,0cyclictest0-21swapper/1511:14:157
2554861991040,103cyclictest2654673-21meminfo08:50:200
25548729910316,45cyclictest2828595-21wine_sechost_se11:46:3215
255486399970,95cyclictest2873115-21meminfo12:30:258
255487699950,94cyclictest2832214-21meminfo11:50:235
255486699955,90cyclictest0-21swapper/511:46:3111
255487699920,91cyclictest2852353-21meminfo12:10:245
255486599920,91cyclictest2679476-21meminfo09:15:2410
255487699910,90cyclictest2679474-21meminfo09:15:245
255486899910,89cyclictest2582694-21meminfo07:35:2112
255487299890,88cyclictest2783341-21meminfo11:00:2415
255486999890,88cyclictest2729125-21meminfo10:05:2213
2554866998749,26cyclictest0-21swapper/511:14:1411
255486399870,86cyclictest2557283-21meminfo07:10:198
255487499860,85cyclictest2674682-21meminfo09:10:303
255487599840,82cyclictest2827233-21meminfo11:45:234
255487499840,83cyclictest2797826-21meminfo11:15:263
255486399830,82cyclictest2748606-21meminfo10:25:228
255486299830,82cyclictest2631162-21meminfo08:25:211
255486299800,78cyclictest2699391-21meminfo09:35:221
255487199790,78cyclictest2689779-21meminfo09:25:2114
255487199790,78cyclictest2684396-21meminfo09:20:2114
255487299780,77cyclictest2738512-21meminfo10:15:2115
255486599780,77cyclictest2709111-21meminfo09:45:2110
255486299780,76cyclictest2738510-21meminfo10:15:211
255487199770,76cyclictest2783343-21meminfo11:00:2414
255486599770,76cyclictest2694633-21meminfo09:30:2110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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