You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-04 - 12:13
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Thu Jul 03, 2025 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74500399436430,5cyclictest2518112-21kworker/0:1+events10:32:490
74500399429424,4cyclictest2518112-21kworker/0:1+events12:37:010
74500399428422,5cyclictest16533-21WebrtcC~read0
74500399427423,3cyclictest0-21swapper/008:53:300
74500399427422,4cyclictest0-21swapper/010:13:210
74500399427420,5cyclictest910634-21kworker/u64:0+events_unbound10:42:170
74500399427420,5cyclictest910634-21kworker/u64:0+events_unbound10:42:170
74500399427418,7cyclictest769547-21kworker/u64:4+events_unbound07:37:450
74502099426424,1cyclictest0-21swapper/1412:11:286
74500399426422,3cyclictest0-21swapper/009:55:250
74500399426419,6cyclictest888374-21kworker/u64:2+events_unbound10:58:450
74500399426419,6cyclictest846889-21kworker/u64:6+events_unbound09:05:150
74502099425424,0cyclictest0-21swapper/1410:50:476
745020994250,0cyclictest0-21swapper/1410:43:346
745020994250,0cyclictest0-21swapper/1410:43:336
745020994250,0cyclictest0-21swapper/1410:11:166
745020994250,0cyclictest0-21swapper/1409:55:266
745020994250,0cyclictest0-21swapper/1408:53:306
74500399425419,5cyclictest888374-21kworker/u64:2+events_unbound11:06:320
74502099424423,0cyclictest0-21swapper/1411:00:056
74502099424422,1cyclictest0-21swapper/1410:09:406
74500699424421,2cyclictest8488-21Compositor07:36:358
74500399424421,3cyclictest0-21swapper/012:32:220
74500399424421,3cyclictest0-21swapper/012:15:370
74500399424421,2cyclictest0-21swapper/008:19:010
74500399424420,3cyclictest0-21swapper/010:35:130
74500399424419,4cyclictest1011845-21kworker/u64:0+events_unbound12:27:480
74500399424418,5cyclictest888374-21kworker/u64:2+events_unbound11:24:270
74500399424418,5cyclictest860106-21kworker/u64:1+events_unbound10:02:480
74500399424418,5cyclictest1001790-21kworker/u64:2+events_unbound12:20:490
74502099423422,0cyclictest0-21swapper/1412:15:366
74502099423422,0cyclictest0-21swapper/1407:36:356
745020994230,0cyclictest0-21swapper/1411:24:536
74500399423419,3cyclictest0-21swapper/009:43:490
74502099422421,0cyclictest0-21swapper/1410:31:026
74502099422421,0cyclictest0-21swapper/1409:54:226
74502099422421,0cyclictest0-21swapper/1407:44:006
74500399422418,4cyclictest0-21swapper/010:47:420
74500399422418,4cyclictest0-21swapper/010:47:420
74502099421420,0cyclictest0-21swapper/1411:29:136
74500699420420,0cyclictest0-21swapper/209:54:218
74500399420417,2cyclictest0-21swapper/012:11:270
74500399420417,2cyclictest0-21swapper/010:50:470
74500399420413,5cyclictest769547-21kworker/u64:4+events_unbound07:44:000
74502099419419,0cyclictest0-21swapper/1410:56:596
74501999419414,4cyclictest7347-21Xorg12:11:105
74500399419416,2cyclictest0-21swapper/011:00:050
74500399419414,5cyclictest0-21swapper/009:54:220
74501999418417,1cyclictest0-21swapper/1309:54:215
74500399418413,3cyclictest888374-21kworker/u64:2+events_unbound11:29:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional