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2024-05-20 - 16:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot3.osadl.org (updated Mon May 20, 2024 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
203009799180,11cyclictest0-21swapper/308:40:133
203009799110,8cyclictest0-21swapper/311:55:253
203009799110,11cyclictest0-21swapper/310:00:143
203009799110,11cyclictest0-21swapper/307:30:123
203009799110,0cyclictest0-21swapper/310:05:143
203009799110,0cyclictest0-21swapper/307:10:103
2030097991010,0cyclictest0-21swapper/310:25:003
2030097991010,0cyclictest0-21swapper/309:15:263
2030097991010,0cyclictest0-21swapper/308:30:163
203009799100,10cyclictest0-21swapper/312:30:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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