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2026-04-18 - 14:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot3.osadl.org (updated Sat Apr 18, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1971952991313,0cyclictest0-21swapper/308:30:193
197195299130,11cyclictest0-21swapper/308:50:133
1971952991212,0cyclictest0-21swapper/311:20:183
1971952991211,0cyclictest0-21swapper/309:40:193
197195299120,11cyclictest0-21swapper/309:50:243
197195299120,11cyclictest0-21swapper/309:00:183
197195299120,11cyclictest0-21swapper/309:00:183
197195299120,10cyclictest0-21swapper/311:55:123
1971952991111,0cyclictest0-21swapper/311:25:183
1971952991111,0cyclictest0-21swapper/309:30:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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