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2024-07-27 - 04:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sat Jul 27, 2024 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31736499456456,0cyclictest0-21swapper/319:19:553
317364991311,1cyclictest0-21swapper/319:25:133
31736499130,10cyclictest0-21swapper/319:20:143
31736499128,1cyclictest0-21swapper/323:00:123
31736499120,11cyclictest0-21swapper/321:50:023
31736499120,11cyclictest0-21swapper/321:15:113
31736499120,11cyclictest0-21swapper/320:20:113
31736499120,11cyclictest0-21swapper/319:55:123
31736499120,11cyclictest0-21swapper/300:30:113
31736499119,0cyclictest0-21swapper/319:45:103
317364991111,0cyclictest0-21swapper/322:45:113
31736499110,11cyclictest0-21swapper/319:35:113
31736499110,10cyclictest0-21swapper/323:30:133
31736499110,0cyclictest0-21swapper/323:40:093
31736499110,0cyclictest0-21swapper/322:35:143
31736499110,0cyclictest0-21swapper/322:05:263
31736499110,0cyclictest0-21swapper/320:50:113
31736499110,0cyclictest0-21swapper/320:40:133
317364991010,0cyclictest0-21swapper/323:55:223
317364991010,0cyclictest0-21swapper/322:20:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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