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2026-06-08 - 00:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Sun Jun 07, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
361477099140,12cyclictest0-21swapper/310:40:113
361477099130,1cyclictest0-21swapper/312:20:123
361477099130,11cyclictest0-21swapper/308:35:123
361477099120,11cyclictest0-21swapper/308:10:003
361477099120,11cyclictest0-21swapper/307:15:003
36225382110,10sleep30-21swapper/307:26:223
361477099119,1cyclictest0-21swapper/310:00:113
3614770991111,0cyclictest0-21swapper/308:44:353
361477099110,10cyclictest0-21swapper/311:50:133
361477099110,10cyclictest0-21swapper/309:54:563
361477099110,0cyclictest0-21swapper/312:30:133
361477099109,0cyclictest0-21swapper/310:55:123
361477099109,0cyclictest0-21swapper/309:15:133
361477099107,2cyclictest0-21swapper/310:10:103
3614770991010,0cyclictest0-21swapper/311:35:173
3614770991010,0cyclictest0-21swapper/310:30:173
3614770991010,0cyclictest0-21swapper/310:25:113
3614770991010,0cyclictest0-21swapper/307:50:003
361477099100,9cyclictest0-21swapper/310:20:123
361477099100,9cyclictest0-21swapper/308:10:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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