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2025-03-17 - 08:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Mon Mar 17, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1508496991311,1cyclictest0-21swapper/321:30:093
150849699130,1cyclictest0-21swapper/322:35:113
150849699130,11cyclictest0-21swapper/323:35:133
150849699130,11cyclictest0-21swapper/322:40:143
150849699120,11cyclictest0-21swapper/323:40:203
150849699120,11cyclictest0-21swapper/322:10:003
150849699120,11cyclictest0-21swapper/321:00:293
150849699120,11cyclictest0-21swapper/320:50:003
150849699120,11cyclictest0-21swapper/320:39:023
150849699120,11cyclictest0-21swapper/319:10:183
1508496991111,0cyclictest0-21swapper/323:00:183
1508496991110,0cyclictest0-21swapper/321:05:183
1508496991110,0cyclictest0-21swapper/320:55:113
1508496991110,0cyclictest0-21swapper/319:50:083
150849699110,11cyclictest0-21swapper/321:50:013
150849699110,11cyclictest0-21swapper/300:15:013
150849699110,10cyclictest0-21swapper/319:30:223
150849699110,0cyclictest0-21swapper/321:35:153
150849699110,0cyclictest0-21swapper/319:25:113
150849699110,0cyclictest0-21swapper/300:15:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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