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2025-07-17 - 20:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Thu Jul 17, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
90780399171,13cyclictest0-21swapper/312:35:163
90780399159,5cyclictest0-21swapper/311:05:113
907803991413,0cyclictest0-21swapper/312:20:533
907803991413,0cyclictest0-21swapper/310:51:483
907803991413,0cyclictest0-21swapper/307:56:413
90780399137,0cyclictest0-21swapper/308:00:153
907803991313,0cyclictest0-21swapper/312:06:323
907803991313,0cyclictest0-21swapper/311:49:093
907803991313,0cyclictest0-21swapper/310:41:333
907803991313,0cyclictest0-21swapper/310:34:233
907803991313,0cyclictest0-21swapper/309:59:343
907803991313,0cyclictest0-21swapper/309:32:563
907803991313,0cyclictest0-21swapper/309:17:353
907803991313,0cyclictest0-21swapper/309:04:163
907803991313,0cyclictest0-21swapper/308:46:513
907803991313,0cyclictest0-21swapper/308:42:473
907803991313,0cyclictest0-21swapper/308:34:343
907803991312,0cyclictest0-21swapper/311:59:233
907803991312,0cyclictest0-21swapper/311:39:553
90780399130,1cyclictest0-21swapper/311:25:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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