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2024-04-19 - 08:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Fri Apr 19, 2024 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100815499142,11cyclictest0-21swapper/322:40:133
100815499129,1cyclictest0-21swapper/300:25:123
100815499120,11cyclictest0-21swapper/300:15:013
1008154991111,0cyclictest0-21swapper/322:20:113
1008154991111,0cyclictest0-21swapper/321:20:013
1008154991110,1cyclictest0-21swapper/323:32:143
100815499110,11cyclictest0-21swapper/322:19:523
100815499110,0cyclictest0-21swapper/319:55:093
100815499110,0cyclictest0-21swapper/300:05:143
1008154991010,0cyclictest0-21swapper/323:45:173
1008154991010,0cyclictest0-21swapper/320:50:013
100815499100,10cyclictest0-21swapper/323:20:113
100815499100,10cyclictest0-21swapper/320:45:013
100815499100,10cyclictest0-21swapper/320:05:163
100815499100,10cyclictest0-21swapper/319:30:233
100815499100,0cyclictest0-21swapper/322:35:013
100815499100,0cyclictest0-21swapper/322:25:073
100815499100,0cyclictest0-21swapper/321:55:223
100815499100,0cyclictest0-21swapper/320:55:173
100815499100,0cyclictest0-21swapper/320:30:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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