You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-15 - 22:33
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Tue Jul 15, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
717189991413,0cyclictest0-21swapper/312:14:133
717189991413,0cyclictest0-21swapper/307:25:273
71718999140,12cyclictest0-21swapper/309:35:153
717189991313,0cyclictest0-21swapper/311:47:363
717189991313,0cyclictest0-21swapper/311:37:213
717189991313,0cyclictest0-21swapper/310:40:003
717189991313,0cyclictest0-21swapper/308:50:273
717189991313,0cyclictest0-21swapper/308:50:263
717189991313,0cyclictest0-21swapper/308:48:233
717189991312,0cyclictest0-21swapper/312:22:263
717189991312,0cyclictest0-21swapper/308:19:433
71718999130,12cyclictest0-21swapper/310:05:143
71718999130,11cyclictest0-21swapper/307:35:123
71718999129,1cyclictest0-21swapper/312:35:123
717189991212,0cyclictest0-21swapper/312:19:203
717189991212,0cyclictest0-21swapper/311:44:323
717189991212,0cyclictest0-21swapper/311:02:333
717189991212,0cyclictest0-21swapper/310:52:183
717189991212,0cyclictest0-21swapper/310:18:303
717189991212,0cyclictest0-21swapper/310:02:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional