You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-04-18 - 18:15
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Thu Apr 18, 2024 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1633728991211,1cyclictest0-21swapper/308:55:113
163372899120,1cyclictest0-21swapper/312:35:143
163372899120,12cyclictest0-21swapper/310:20:323
163372899120,11cyclictest0-21swapper/312:30:113
163372899120,11cyclictest0-21swapper/308:00:123
163372899120,0cyclictest0-21swapper/309:15:133
1633728991111,0cyclictest0-21swapper/307:50:013
1633728991111,0cyclictest0-21swapper/307:38:253
163372899110,8cyclictest0-21swapper/312:20:153
163372899110,11cyclictest0-21swapper/308:45:023
163372899110,11cyclictest0-21swapper/308:45:013
163372899110,10cyclictest0-21swapper/309:25:113
163372899110,0cyclictest0-21swapper/309:10:183
1633728991010,0cyclictest0-21swapper/311:20:113
1633728991010,0cyclictest0-21swapper/310:35:143
1633728991010,0cyclictest0-21swapper/310:25:143
1633728991010,0cyclictest0-21swapper/309:50:003
1633728991010,0cyclictest0-21swapper/308:05:113
163372899100,0cyclictest0-21swapper/312:10:263
163372899100,0cyclictest0-21swapper/311:30:203
163372899100,0cyclictest0-21swapper/311:15:133
163372899100,0cyclictest0-21swapper/310:40:203
163372899100,0cyclictest0-21swapper/308:30:193
16337289999,0cyclictest0-21swapper/310:55:503
16337289999,0cyclictest0-21swapper/310:30:223
16337289990,9cyclictest0-21swapper/311:55:223
16337289990,9cyclictest0-21swapper/310:10:223
16337289990,9cyclictest0-21swapper/307:50:103
16337289990,0cyclictest0-21swapper/311:25:123
16337289990,0cyclictest0-21swapper/311:06:513
16337289988,0cyclictest0-21swapper/312:05:113
16337289988,0cyclictest0-21swapper/309:50:163
16337289988,0cyclictest0-21swapper/307:55:223
16337289980,8cyclictest0-21swapper/311:50:013
16337289980,8cyclictest0-21swapper/307:25:003
16337289980,0cyclictest0-21swapper/307:40:183
16337289977,0cyclictest0-21swapper/311:55:013
16337289977,0cyclictest0-21swapper/309:55:223
16337289977,0cyclictest0-21swapper/309:23:233
16337289976,0cyclictest0-21swapper/307:15:123
16337289970,7cyclictest0-21swapper/311:35:213
16337289970,7cyclictest0-21swapper/309:40:203
16337289970,7cyclictest0-21swapper/308:25:223
16337289970,7cyclictest0-21swapper/308:15:113
1632631272,3sleep10-21swapper/107:05:181
13129870,3rtkit-daemon617-21gmain07:05:470
16337289966,0cyclictest0-21swapper/312:00:573
16337289966,0cyclictest0-21swapper/311:04:293
16337289962,4cyclictest0-21swapper/310:45:103
16337289960,6cyclictest0-21swapper/311:15:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional