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2021-01-26 - 05:37

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 5.4.17-rt9 (Profile)

Latency plot of system in rack #1, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Tue May 26, 2020 00:45:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149122550,2sleep09-21ksoftirqd/022:55:020
329525344,6sleep40-21swapper/419:06:074
353624938,7sleep10-21swapper/119:09:331
350324838,7sleep60-21swapper/619:09:066
348224837,7sleep30-21swapper/319:08:473
325024744,2sleep50-21swapper/519:05:285
355124536,6sleep70-21swapper/719:09:477
336024534,7sleep20-21swapper/219:07:022
347924334,6sleep00-21swapper/019:08:440
167542430,0sleep50-21swapper/500:05:075
211652400,0sleep10-21swapper/122:00:031
377999170,16cyclictest0-21swapper/522:30:095
377499160,16cyclictest0-21swapper/423:20:014
377999140,13cyclictest0-21swapper/500:15:025
376899130,12cyclictest0-21swapper/300:05:023
3763991311,1cyclictest0-21swapper/200:15:072
376399130,0cyclictest0-21swapper/221:10:022
3758991312,1cyclictest0-21swapper/119:35:031
378999120,0cyclictest0-21swapper/719:55:017
3774991212,0cyclictest0-21swapper/419:25:014
376399120,0cyclictest0-21swapper/200:00:022
375399120,0cyclictest0-21swapper/000:00:080
3768991111,0cyclictest0-21swapper/320:00:063
3763991111,0cyclictest0-21swapper/223:10:092
109662110,0sleep0101rcuc/019:25:000
3784991010,0cyclictest0-21swapper/619:25:056
3774991010,0cyclictest0-21swapper/422:00:014
3774991010,0cyclictest0-21swapper/421:45:024
3753991010,0cyclictest0-21swapper/000:20:000
37899998,1cyclictest0-21swapper/720:45:097
37849999,0cyclictest0-21swapper/600:10:086
37849998,1cyclictest56-21ksoftirqd/623:28:126
37689994,4cyclictest7753-21tr22:40:023
37689990,6cyclictest205371latency_hist22:00:003
37689990,0cyclictest0-21swapper/323:08:313
37689990,0cyclictest0-21swapper/322:17:503
37689990,0cyclictest0-21swapper/321:50:573
37689990,0cyclictest0-21swapper/300:34:563
37689990,0cyclictest0-21swapper/300:11:443
37589999,0cyclictest0-21swapper/120:50:041
37539999,0cyclictest0-21swapper/023:19:550
37539999,0cyclictest0-21swapper/021:14:160
37539990,9cyclictest0-21swapper/020:24:550
37899988,0cyclictest0-21swapper/722:39:187
37899988,0cyclictest0-21swapper/719:10:057
37899980,8cyclictest0-21swapper/722:58:047
37899980,8cyclictest0-21swapper/720:35:327
37899980,8cyclictest0-21swapper/720:35:327
37899980,0cyclictest0-21swapper/721:49:197
37849987,1cyclictest0-21swapper/623:55:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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