You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-12 - 01:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Wed Feb 11, 2026 12:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
79013299140,12cyclictest0-21swapper/309:25:123
790132991312,0cyclictest0-21swapper/309:50:113
790132991311,1cyclictest0-21swapper/312:35:123
79013299120,11cyclictest0-21swapper/310:55:023
79013299120,11cyclictest0-21swapper/309:35:023
79013299120,11cyclictest0-21swapper/307:55:003
79013299120,10cyclictest0-21swapper/310:15:113
790132991111,0cyclictest0-21swapper/311:05:003
790132991111,0cyclictest0-21swapper/309:20:173
790132991111,0cyclictest0-21swapper/307:15:183
79013299110,11cyclictest0-21swapper/309:35:183
79013299110,10cyclictest0-21swapper/312:00:203
79013299110,10cyclictest0-21swapper/309:00:013
79013299110,10cyclictest0-21swapper/307:35:173
79013299110,10cyclictest0-21swapper/307:25:193
79013299110,0cyclictest0-21swapper/311:25:003
79013299110,0cyclictest0-21swapper/310:57:583
79013299110,0cyclictest0-21swapper/310:10:123
79013299110,0cyclictest0-21swapper/308:10:193
140398110,2rtkit-daemon0-21swapper/207:05:282
79013299109,0cyclictest0-21swapper/310:30:123
790132991010,0cyclictest0-21swapper/312:25:183
790132991010,0cyclictest0-21swapper/311:30:123
79013299100,9cyclictest0-21swapper/312:30:133
79013299100,9cyclictest0-21swapper/312:15:193
79013299100,9cyclictest0-21swapper/312:00:013
79013299100,9cyclictest0-21swapper/307:30:133
79013299100,10cyclictest0-21swapper/311:05:183
79013299100,10cyclictest0-21swapper/308:15:193
79013299100,0cyclictest0-21swapper/309:40:123
79013299100,0cyclictest0-21swapper/307:10:113
7901329999,0cyclictest0-21swapper/311:45:193
7901329999,0cyclictest0-21swapper/310:25:183
7901329999,0cyclictest0-21swapper/308:35:203
7901329988,0cyclictest0-21swapper/312:20:103
7901329988,0cyclictest0-21swapper/312:13:013
7901329988,0cyclictest0-21swapper/311:35:163
7901329988,0cyclictest0-21swapper/311:12:593
7901329988,0cyclictest0-21swapper/310:00:013
7901329988,0cyclictest0-21swapper/308:20:123
7901329987,0cyclictest0-21swapper/310:25:013
7901329980,0cyclictest0-21swapper/309:05:173
788450281,5sleep30-21swapper/307:05:153
7901329977,0cyclictest0-21swapper/308:50:153
7901329977,0cyclictest0-21swapper/308:40:143
7901329977,0cyclictest0-21swapper/307:55:003
7901329976,0cyclictest0-21swapper/310:35:133
7901329976,0cyclictest0-21swapper/310:00:173
7901329976,0cyclictest0-21swapper/307:20:113
789191270,5sleep0789288-21ls07:05:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional