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2024-09-08 - 10:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Sun Sep 08, 2024 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
95178499120,11cyclictest0-21swapper/320:10:123
95178499120,0cyclictest0-21swapper/319:40:123
951784991111,0cyclictest0-21swapper/320:49:223
95178499110,1cyclictest0-21swapper/319:20:183
95178499110,11cyclictest0-21swapper/323:55:003
95178499110,11cyclictest0-21swapper/322:55:123
95178499110,10cyclictest0-21swapper/319:50:123
95178499110,0cyclictest0-21swapper/320:30:173
951784991010,0cyclictest0-21swapper/323:35:013
951784991010,0cyclictest0-21swapper/321:20:133
95178499100,10cyclictest0-21swapper/319:45:163
95178499100,10cyclictest0-21swapper/319:14:553
95178499100,0cyclictest0-21swapper/323:45:143
95178499100,0cyclictest0-21swapper/321:05:193
95178499100,0cyclictest0-21swapper/320:25:013
95178499100,0cyclictest0-21swapper/300:34:563
9517849999,0cyclictest0-21swapper/322:34:383
9517849999,0cyclictest0-21swapper/321:15:183
9517849999,0cyclictest0-21swapper/319:55:113
9517849999,0cyclictest0-21swapper/300:10:003
9517849990,9cyclictest0-21swapper/300:35:183
9517849990,0cyclictest0-21swapper/320:40:133
9517849988,0cyclictest0-21swapper/323:15:013
9517849988,0cyclictest0-21swapper/323:05:113
9517849988,0cyclictest0-21swapper/322:44:563
9517849988,0cyclictest0-21swapper/322:15:133
9517849988,0cyclictest0-21swapper/320:35:123
9517849980,8cyclictest0-21swapper/322:00:013
9517849980,8cyclictest0-21swapper/319:30:163
9517849980,0cyclictest0-21swapper/300:20:183
9517849977,0cyclictest0-21swapper/323:22:563
9517849977,0cyclictest0-21swapper/323:20:013
9517849977,0cyclictest0-21swapper/323:05:013
9517849977,0cyclictest0-21swapper/321:55:013
9517849977,0cyclictest0-21swapper/320:55:123
9517849977,0cyclictest0-21swapper/320:05:133
9517849977,0cyclictest0-21swapper/300:15:243
9517849970,3cyclictest0-21swapper/319:25:393
9517849970,0cyclictest0-21swapper/323:31:083
9517849966,0cyclictest0-21swapper/322:20:123
9517849960,6cyclictest0-21swapper/323:45:013
9517849955,0cyclictest0-21swapper/322:27:343
9517849955,0cyclictest0-21swapper/321:49:493
9517849955,0cyclictest0-21swapper/321:38:183
9517849955,0cyclictest0-21swapper/321:38:173
9517849955,0cyclictest0-21swapper/321:00:133
9517849953,1cyclictest0-21swapper/300:25:143
9517849950,5cyclictest0-21swapper/322:00:183
9517849950,4cyclictest0-21swapper/320:15:133
949949251,3sleep30-21swapper/319:05:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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