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2022-01-23 - 09:43

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sun Jan 23, 2022 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69512490,0sleep00-21swapper/021:10:040
69512490,0sleep00-21swapper/021:10:040
2858524230,8sleep70-21swapper/718:58:007
2858524230,8sleep70-21swapper/718:58:007
2843224129,8sleep50-21swapper/518:55:585
2843224129,8sleep50-21swapper/518:55:585
2840924128,9sleep20-21swapper/218:55:392
2840924128,9sleep20-21swapper/218:55:392
2839824129,8sleep00-21swapper/018:55:290
2839824129,8sleep00-21swapper/018:55:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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