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2025-07-12 - 08:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Jul 12, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
143852810,0sleep3391rcuc/321:51:183
249582710,0sleep20-21swapper/222:32:102
67352550,0sleep40-21swapper/423:58:534
101232530,0sleep50-21swapper/523:50:385
152632510,0sleep00-21swapper/023:11:160
86222500,0sleep70-21swapper/722:12:127
85212490,1sleep6668-21systemd-logind23:59:036
325124825,9sleep40-21swapper/418:58:154
76092470,0sleep00-21swapper/021:02:460
63702470,1sleep5859-21polkitd21:24:055
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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