You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-10-05 - 14:04
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot0.osadl.org (updated Sat Oct 05, 2024 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
828021010,0sleep21-21systemd12:29:172
313702840,0sleep059599cyclictest09:44:490
303962570,0sleep1241ktimersoftd/110:16:211
32002530,0sleep50-21swapper/512:16:225
3273124824,8sleep00-21swapper/007:06:350
276412470,0sleep20-21swapper/211:43:122
220352470,0sleep70-21swapper/710:28:287
215292460,0sleep00-21swapper/011:10:020
154052460,0sleep10-21swapper/112:05:451
147352460,0sleep20-21swapper/211:17:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional