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2021-06-17 - 19:37

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot0.osadl.org (updated Thu Jun 17, 2021 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
579524925,8sleep00-21swapper/007:03:510
584024724,8sleep50-21swapper/507:04:295
588524027,9sleep30-21swapper/307:05:073
582024029,8sleep70-21swapper/707:04:147
581724028,9sleep40-21swapper/407:04:114
578724028,9sleep10-21swapper/107:03:441
359224028,8sleep60-21swapper/607:02:456
403523824,9sleep20-21swapper/207:02:572
6200992421,0cyclictest0-21swapper/507:17:585
619699210,16cyclictest0-21swapper/112:23:051
619899200,17cyclictest0-21swapper/310:23:053
620299190,13cyclictest0-21swapper/710:26:147
619999190,13cyclictest0-21swapper/410:54:184
619799191,12cyclictest0-21swapper/207:43:302
619799190,13cyclictest0-21swapper/208:42:112
620299183,12cyclictest0-21swapper/710:20:567
620299183,12cyclictest0-21swapper/710:20:567
620099183,15cyclictest0-21swapper/509:54:255
619999180,17cyclictest0-21swapper/408:48:004
619699180,15cyclictest0-21swapper/111:32:311
618899180,17cyclictest0-21swapper/010:03:020
618899180,13cyclictest0-21swapper/008:17:160
618899180,12cyclictest0-21swapper/012:33:020
620299172,14cyclictest20844-21ntp_states09:23:007
620299170,17cyclictest0-21swapper/712:26:507
620199170,17cyclictest0-21swapper/608:04:076
620199170,17cyclictest0-21swapper/608:04:076
620199170,16cyclictest0-21swapper/612:32:576
620199170,16cyclictest0-21swapper/608:43:036
620099172,15cyclictest0-21swapper/511:56:585
6200991715,2cyclictest0-21swapper/509:35:425
620099170,17cyclictest0-21swapper/510:13:325
620099170,17cyclictest0-21swapper/507:45:455
6199991717,0cyclictest0-21swapper/407:38:004
619999170,17cyclictest0-21swapper/411:51:104
619999170,17cyclictest0-21swapper/410:23:504
619899172,15cyclictest0-21swapper/311:33:013
619899170,17cyclictest0-21swapper/312:05:023
619899170,17cyclictest0-21swapper/311:43:053
619899170,17cyclictest0-21swapper/309:31:063
619799173,14cyclictest0-21swapper/210:42:482
619799172,15cyclictest0-21swapper/211:45:282
619799172,15cyclictest0-21swapper/209:38:252
619799172,12cyclictest0-21swapper/208:37:232
619799170,17cyclictest0-21swapper/210:17:022
619799170,17cyclictest0-21swapper/208:48:112
619699172,15cyclictest0-21swapper/111:17:071
619699172,15cyclictest0-21swapper/110:49:241
619699172,15cyclictest0-21swapper/109:16:541
619699172,15cyclictest0-21swapper/109:16:541
619699172,12cyclictest0-21swapper/110:53:301
619699170,17cyclictest0-21swapper/112:09:021
619699170,17cyclictest0-21swapper/110:41:241
619699170,17cyclictest0-21swapper/110:12:111
619699170,17cyclictest0-21swapper/108:32:561
619699170,17cyclictest0-21swapper/107:47:571
619699170,12cyclictest0-21swapper/109:06:481
618899170,17cyclictest0-21swapper/010:35:440
618899170,16cyclictest18816-21latency11:13:000
618899170,16cyclictest0-21swapper/012:23:020
620299161,12cyclictest0-21swapper/710:38:337
620299161,12cyclictest0-21swapper/708:04:437
620299161,12cyclictest0-21swapper/708:04:437
620299160,16cyclictest0-21swapper/711:49:437
620299160,16cyclictest0-21swapper/711:13:227
620299160,16cyclictest0-21swapper/710:28:147
620299160,16cyclictest0-21swapper/707:26:267
620299160,16cyclictest0-21swapper/707:15:567
620299160,13cyclictest0-21swapper/710:08:107
620299160,13cyclictest0-21swapper/709:44:407
620299160,13cyclictest0-21swapper/708:51:387
620299160,13cyclictest0-21swapper/708:12:377
620199160,16cyclictest0-21swapper/608:27:586
620199160,14cyclictest0-21swapper/608:40:176
620199160,13cyclictest0-21swapper/611:55:046
620199160,13cyclictest0-21swapper/611:28:556
620199160,13cyclictest0-21swapper/609:42:496
620199160,13cyclictest0-21swapper/607:48:096
620199160,13cyclictest0-21swapper/607:47:096
620099160,16cyclictest0-21swapper/511:10:065
620099160,16cyclictest0-21swapper/510:28:025
620099160,16cyclictest0-21swapper/508:03:015
620099160,16cyclictest0-21swapper/508:03:015
620099160,13cyclictest0-21swapper/512:06:145
620099160,13cyclictest0-21swapper/510:48:155
620099160,13cyclictest0-21swapper/508:39:475
619999162,14cyclictest0-21swapper/408:26:224
619999160,16cyclictest0-21swapper/412:28:264
619999160,16cyclictest0-21swapper/412:19:264
619999160,16cyclictest0-21swapper/411:42:434
619999160,16cyclictest0-21swapper/411:01:094
619999160,16cyclictest0-21swapper/410:43:334
619999160,16cyclictest0-21swapper/409:28:514
619999160,13cyclictest0-21swapper/409:54:374
619899160,16cyclictest0-21swapper/311:11:243
619899160,16cyclictest0-21swapper/310:05:463
619899160,16cyclictest0-21swapper/310:01:403
619899160,16cyclictest0-21swapper/309:39:253
619899160,16cyclictest0-21swapper/309:20:183
619899160,16cyclictest0-21swapper/309:20:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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