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2025-05-24 - 11:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Sat May 24, 2025 00:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
167532810,2sleep72591199cyclictest22:42:467
243982740,0sleep70-21swapper/721:40:237
91732530,0sleep00-21swapper/022:10:360
2555025247,2sleep60-21swapper/618:58:166
159462510,0sleep40-21swapper/423:08:544
286702490,0sleep40-21swapper/422:01:354
25362480,0sleep1763-21runrttasks22:52:021
312392470,0sleep60-21swapper/622:22:436
148452470,0sleep70-21swapper/723:24:357
59522460,0sleep50-21swapper/500:05:425
2573724624,8sleep00-21swapper/019:00:500
246962450,2sleep52589799cyclictest23:04:235
208872450,2sleep22587699cyclictest21:06:152
218692440,0sleep2321ktimersoftd/200:13:402
15682440,0sleep50-21swapper/522:44:135
295452430,0sleep50-21swapper/521:53:515
51332420,2sleep52589799cyclictest00:11:425
287902410,2sleep52589799cyclictest21:40:465
2573924128,9sleep20-21swapper/219:00:522
2560524128,9sleep30-21swapper/318:59:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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