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2024-02-25 - 12:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Sun Feb 25, 2024 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
774125629,22sleep70-21swapper/719:04:127
774125629,22sleep70-21swapper/719:04:127
880624725,8sleep40-21swapper/419:06:414
880624725,8sleep40-21swapper/419:06:414
870224724,8sleep50-21swapper/519:05:145
870224724,8sleep50-21swapper/519:05:145
865424229,9sleep60-21swapper/619:04:356
865424229,9sleep60-21swapper/619:04:356
864924230,8sleep10-21swapper/119:04:301
864924230,8sleep10-21swapper/119:04:301
887024129,8sleep20-21swapper/219:07:352
887024129,8sleep20-21swapper/219:07:352
874924027,9sleep30-21swapper/319:05:523
874924027,9sleep30-21swapper/319:05:523
867924028,8sleep00-21swapper/019:04:530
867924028,8sleep00-21swapper/019:04:530
313952400,0sleep1231rcuc/122:34:011
313952400,0sleep1231rcuc/122:34:011
907299226,6cyclictest13162-21kworker/3:321:28:493
907299226,6cyclictest13162-21kworker/3:321:28:493
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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