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2022-11-29 - 15:28

x86 Intel Xeon E3-1270 v2 @3500 MHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Tue Nov 29, 2022 12:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1631624924,8sleep50-21swapper/507:02:305
1631624924,8sleep50-21swapper/507:02:305
239142470,0sleep7721ktimersoftd/711:38:107
239142470,0sleep7721ktimersoftd/711:38:107
1857524230,9sleep40-21swapper/407:03:254
1857524230,9sleep40-21swapper/407:03:254
1875524128,9sleep70-21swapper/707:05:537
1875524128,9sleep70-21swapper/707:05:537
19922400,0sleep20-21swapper/209:47:292
19922400,0sleep20-21swapper/209:47:292
1876724027,9sleep00-21swapper/007:06:020
1876724027,9sleep00-21swapper/007:06:020
1859223927,8sleep30-21swapper/307:03:403
1859223927,8sleep30-21swapper/307:03:403
1804823923,11sleep10-21swapper/107:02:501
1804823923,11sleep10-21swapper/107:02:501
1857323827,8sleep20-21swapper/207:03:232
1857323827,8sleep20-21swapper/207:03:232
1855923826,8sleep60-21swapper/607:03:116
1855923826,8sleep60-21swapper/607:03:116
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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