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2024-12-10 - 06:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Tue Dec 10, 2024 00:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263092460,0sleep40-21swapper/422:19:074
114972460,0sleep00-21swapper/023:31:590
147872450,0sleep60-21swapper/600:15:386
73572440,0sleep40-21swapper/421:48:564
52652440,0sleep50-21swapper/523:54:235
2651524431,9sleep60-21swapper/619:03:156
2651524431,9sleep60-21swapper/619:03:156
138982440,0sleep20-21swapper/223:04:462
279712420,0sleep30-21swapper/323:06:313
49252410,0sleep10-21swapper/121:20:021
319102410,0sleep40-21swapper/400:22:014
318872410,0sleep20-21swapper/222:31:382
318872410,0sleep20-21swapper/222:31:382
297212410,0sleep00-21swapper/021:38:270
2665224128,9sleep30-21swapper/319:05:043
2665224128,9sleep30-21swapper/319:05:043
2665024124,13sleep10-21swapper/119:05:021
2665024124,13sleep10-21swapper/119:05:021
2659624128,9sleep70-21swapper/719:04:207
2659624128,9sleep70-21swapper/719:04:207
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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