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2021-07-26 - 18:32

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Mon Jul 26, 2021 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
237472690,2sleep22575699cyclictest11:41:412
97992520,0sleep60-21swapper/608:31:126
97992520,0sleep60-21swapper/608:31:126
2558724724,9sleep10-21swapper/107:05:401
2558724724,9sleep10-21swapper/107:05:401
142192440,0sleep10-21swapper/112:21:351
2506424229,9sleep40-21swapper/407:01:424
2506424229,9sleep40-21swapper/407:01:424
2483624128,8sleep20-21swapper/207:01:402
2483624128,8sleep20-21swapper/207:01:402
2534324028,8sleep70-21swapper/707:02:177
2534324028,8sleep70-21swapper/707:02:177
2361624027,8sleep00-21swapper/007:01:300
2361624027,8sleep00-21swapper/007:01:300
2556223928,8sleep30-21swapper/307:05:183
2556223928,8sleep30-21swapper/307:05:183
2538923926,9sleep60-21swapper/607:02:576
2538923926,9sleep60-21swapper/607:02:576
2535023927,9sleep50-21swapper/507:02:235
2535023927,9sleep50-21swapper/507:02:235
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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