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2025-07-01 - 00:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Mon Jun 30, 2025 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
241752730,1sleep773-21ksoftirqd/711:25:187
57572710,0sleep30-21swapper/310:31:403
141092700,7sleep70-21swapper/706:54:587
192642600,0sleep20-21swapper/210:45:002
1437925625,18sleep50-21swapper/506:57:215
264292530,0sleep40-21swapper/409:38:394
17722500,1sleep01773-21sshd11:38:240
307312490,1sleep2763-21runrttasks09:44:542
1425124925,9sleep30-21swapper/306:55:353
56522480,1sleep557-21ksoftirqd/509:14:215
312452480,2sleep41471699cyclictest12:07:364
62802470,0sleep20-21swapper/211:04:312
203692470,0sleep70-21swapper/709:47:077
1444324724,9sleep40-21swapper/406:58:174
292582460,0sleep30-21swapper/310:24:513
247492450,0sleep10-21swapper/111:59:481
137542450,0sleep00-21swapper/011:14:060
80452440,0sleep60-21swapper/609:42:586
115322420,0sleep20-21swapper/212:20:472
115322420,0sleep20-21swapper/212:20:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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