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2023-04-01 - 09:50

x86 Intel Xeon E3-1270 v2 @3500 MHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Sat Apr 01, 2023 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
78032700,1sleep67805-21open_inodes19:08:326
78032700,1sleep67805-21open_inodes19:08:326
266924925,9sleep40-21swapper/418:58:534
289124825,8sleep60-21swapper/619:01:526
281624129,8sleep70-21swapper/719:00:497
268824129,9sleep10-21swapper/118:59:071
291024028,8sleep50-21swapper/519:02:075
283024027,9sleep30-21swapper/319:01:013
280724028,8sleep00-21swapper/019:00:420
279023928,8sleep20-21swapper/219:00:282
311099210,6cyclictest0-21swapper/222:09:282
311099210,6cyclictest0-21swapper/222:09:282
311099192,5cyclictest11622-21idleruntime-cro00:13:092
311099192,5cyclictest11622-21idleruntime-cro00:13:092
311099190,10cyclictest1-21systemd21:13:562
311099190,10cyclictest1-21systemd21:13:562
311099180,8cyclictest28980-21systemd22:35:402
311099180,8cyclictest28980-21systemd22:35:402
311099180,7cyclictest4210-21sshd22:42:382
311099180,7cyclictest4210-21sshd22:42:382
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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