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2021-10-24 - 01:52

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Sun Oct 24, 2021 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
68432900,0sleep70-21swapper/720:48:267
950027127,28sleep00-21swapper/019:00:180
952424230,8sleep40-21swapper/419:00:384
945224129,8sleep70-21swapper/718:59:457
946124028,8sleep50-21swapper/518:59:515
947023927,9sleep30-21swapper/318:59:573
943423926,9sleep10-21swapper/118:59:311
943023928,8sleep60-21swapper/618:59:286
940823926,9sleep20-21swapper/218:59:082
280042380,0sleep50-21swapper/522:23:055
9833993111,20cyclictest12195-21kworker/7:022:58:217
983399266,20cyclictest22468-21kworker/7:121:18:197
9822992624,2cyclictest0-21swapper/300:01:593
9822992120,0cyclictest0-21swapper/323:32:313
9822992019,1cyclictest0-21swapper/323:46:233
9822992018,2cyclictest21162-21kworker/3:019:33:093
981999202,15cyclictest0-21swapper/021:25:460
9822991917,2cyclictest17520-21kworker/3:220:14:453
9822991917,2cyclictest17520-21kworker/3:220:14:453
9822991917,2cyclictest17456-21kworker/3:200:29:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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