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2019-07-17 - 00:36

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Tue Jul 16, 2019 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
265462590,0sleep60-21swapper/609:16:426
1803725226,9sleep40-21swapper/407:00:534
1803725226,9sleep40-21swapper/407:00:534
1818125026,9sleep60-21swapper/607:02:476
1818125026,9sleep60-21swapper/607:02:476
63892490,0sleep10-21swapper/111:36:441
1831524925,8sleep00-21swapper/007:04:410
1831524925,8sleep00-21swapper/007:04:410
259802460,0sleep425981-21kworker/u16:312:22:364
259802460,0sleep425981-21kworker/u16:312:22:364
125912460,0sleep50-21swapper/509:46:045
125912460,0sleep50-21swapper/509:46:045
186092440,0sleep40-21swapper/412:00:174
150012440,0sleep10-21swapper/111:27:391
150012440,0sleep10-21swapper/111:27:391
71532420,0sleep50-21swapper/510:17:285
71532420,0sleep50-21swapper/510:17:285
220052420,0sleep70-21swapper/710:09:297
42002410,0sleep10-21swapper/111:20:341
42002410,0sleep10-21swapper/111:20:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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