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2022-06-27 - 16:25

x86 Intel Xeon E3-1270 v2 @3500 MHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot0.osadl.org (updated Mon Jun 27, 2022 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
378599850048850040,8cyclictest0-21swapper/411:29:424
378599850048850040,8cyclictest0-21swapper/411:29:424
378499850047850044,3cyclictest0-21swapper/311:29:423
378499850047850044,3cyclictest0-21swapper/311:29:423
378199850040850034,4cyclictest0-21swapper/011:29:420
378199850040850034,4cyclictest0-21swapper/011:29:420
378899850032850027,4cyclictest0-21swapper/711:29:427
378899850032850027,4cyclictest0-21swapper/711:29:427
378299849995849989,6cyclictest0-21swapper/111:29:421
378299849995849989,6cyclictest0-21swapper/111:29:421
378799849966849960,6cyclictest0-21swapper/611:29:426
378799849966849960,6cyclictest0-21swapper/611:29:426
378399849914849908,6cyclictest0-21swapper/211:29:422
378399849914849908,6cyclictest0-21swapper/211:29:422
378699849894849889,4cyclictest0-21swapper/511:29:425
378699849894849889,4cyclictest0-21swapper/511:29:425
148492480,7sleep665-21ksoftirqd/610:52:546
33782450,0sleep20-21swapper/211:46:242
191352390,0sleep70-21swapper/712:03:277
345523321,8sleep00-21swapper/007:02:030
345523321,8sleep00-21swapper/007:02:030
35742297,8sleep60-21swapper/607:03:386
35742297,8sleep60-21swapper/607:03:386
120722919,7sleep70-21swapper/706:59:467
120722919,7sleep70-21swapper/706:59:467
36332285,8sleep30-21swapper/307:04:233
36332285,8sleep30-21swapper/307:04:233
333522716,8sleep20-21swapper/207:00:212
333522716,8sleep20-21swapper/207:00:212
358722623,1sleep10-21swapper/107:03:491
358722623,1sleep10-21swapper/107:03:491
354222613,9sleep50-21swapper/507:03:135
354222613,9sleep50-21swapper/507:03:135
3785991818,0cyclictest15750irq/23-ehci_hcd11:05:494
3785991818,0cyclictest15750irq/23-ehci_hcd11:05:494
3785991818,0cyclictest0-21swapper/411:40:004
11472185,9sleep40-21swapper/406:59:434
11472185,9sleep40-21swapper/406:59:434
169092170,0sleep10-21swapper/109:14:561
378899147,3cyclictest13331-21kworker/7:212:18:067
378899147,3cyclictest13331-21kworker/7:212:18:067
3784991413,0cyclictest0-21swapper/311:14:383
3784991412,1cyclictest41-21ksoftirqd/308:29:593
3784991412,1cyclictest41-21ksoftirqd/308:29:593
3781991412,1cyclictest28981-21cat11:40:000
3788991311,1cyclictest73-21ksoftirqd/707:24:417
3788991311,1cyclictest73-21ksoftirqd/707:24:417
3785991313,0cyclictest0-21swapper/407:14:284
3785991311,1cyclictest49-21ksoftirqd/408:34:414
3785991311,1cyclictest49-21ksoftirqd/408:34:414
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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