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2023-01-30 - 05:23

x86 Intel Xeon E3-1270 v2 @3500 MHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot0.osadl.org (updated Mon Jan 30, 2023 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3167924625,18sleep30-21swapper/319:05:003
3162324624,8sleep50-21swapper/519:04:145
3157624331,8sleep70-21swapper/719:03:367
3162424027,9sleep60-21swapper/619:04:156
3158924028,8sleep20-21swapper/219:03:472
3145524028,8sleep00-21swapper/019:01:530
3143024028,8sleep40-21swapper/419:01:334
3153223726,8sleep10-21swapper/119:02:581
242102330,0sleep70-21swapper/722:52:297
242102330,0sleep70-21swapper/722:52:297
3180999177,8cyclictest3119-21kworker/7:121:10:167
3180999177,8cyclictest3119-21kworker/7:121:10:167
3180999149,2cyclictest22191-21kworker/7:019:53:527
3180999149,2cyclictest22191-21kworker/7:019:53:527
3180999146,8cyclictest31376-21kworker/7:219:24:007
3180999146,8cyclictest31376-21kworker/7:219:24:007
3180999146,6cyclictest12424-21kworker/7:223:21:127
3180699149,3cyclictest49-21ksoftirqd/421:47:514
3180699149,3cyclictest49-21ksoftirqd/421:47:514
3180599149,2cyclictest3714-21kworker/3:123:27:283
3180599149,2cyclictest14697-21kworker/3:322:50:563
3180599149,2cyclictest14697-21kworker/3:322:50:563
3180599146,6cyclictest31408-21kworker/3:219:21:383
3180599146,6cyclictest31408-21kworker/3:219:21:383
3180599146,6cyclictest24212-21kworker/3:020:45:423
3180599146,5cyclictest31408-21kworker/3:219:12:063
3180599146,5cyclictest31408-21kworker/3:219:12:063
139162140,0sleep10-21swapper/123:15:211
139162140,0sleep10-21swapper/123:15:211
3180999139,0cyclictest31376-21kworker/7:219:13:527
3180999139,0cyclictest31376-21kworker/7:219:13:527
3180999138,2cyclictest22191-21kworker/7:020:44:487
3180999138,2cyclictest22191-21kworker/7:020:31:307
3180999136,6cyclictest24436-21kworker/7:222:07:107
3180999136,6cyclictest24436-21kworker/7:222:07:107
3180999136,5cyclictest22191-21kworker/7:020:46:187
3180999136,5cyclictest22191-21kworker/7:019:45:587
3180999136,5cyclictest14197-21kworker/7:000:19:147
3180999136,5cyclictest14197-21kworker/7:000:19:147
3180999136,2cyclictest22191-21kworker/7:020:12:067
3180999136,2cyclictest22191-21kworker/7:020:12:067
3180999135,6cyclictest31376-21kworker/7:219:15:347
3180999135,6cyclictest31376-21kworker/7:219:15:347
3180999135,6cyclictest31070-21kworker/7:122:14:347
3180999135,6cyclictest31070-21kworker/7:122:14:347
3180999135,6cyclictest30561-21kworker/7:023:01:507
3180999135,6cyclictest30561-21kworker/7:023:01:507
3180999135,6cyclictest22191-21kworker/7:020:50:267
3180999135,6cyclictest22191-21kworker/7:020:20:467
3180999135,6cyclictest22191-21kworker/7:020:03:147
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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