You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2022-01-26 - 11:44

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot0.osadl.org (updated Wed Jan 26, 2022 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2318424433,8sleep20-21swapper/218:58:042
2202624330,9sleep00-21swapper/018:55:140
2322424231,8sleep30-21swapper/318:58:373
2315824229,9sleep50-21swapper/518:57:435
2309224129,8sleep70-21swapper/718:56:497
2305724130,8sleep10-21swapper/118:56:191
2307124028,8sleep60-21swapper/618:56:326
2234424028,8sleep40-21swapper/418:55:264
2343799193,16cyclictest0-21swapper/522:59:435
2343499190,13cyclictest0-21swapper/222:34:362
2343999180,17cyclictest0-21swapper/720:46:037
2343999180,17cyclictest0-21swapper/720:46:037
2343899182,13cyclictest0-21swapper/619:08:426
2343899180,14cyclictest0-21swapper/620:07:416
2343899180,13cyclictest0-21swapper/621:47:176
2343799182,16cyclictest0-21swapper/521:02:515
2343799182,16cyclictest0-21swapper/521:02:515
2343799180,18cyclictest0-21swapper/521:33:465
2343799180,18cyclictest0-21swapper/521:33:465
2343399180,15cyclictest0-21swapper/119:28:401
2343399180,15cyclictest0-21swapper/119:28:401
2343999170,16cyclictest0-21swapper/723:15:007
2343799170,12cyclictest0-21swapper/520:59:035
2343699170,17cyclictest0-21swapper/422:56:074
2343599170,15cyclictest0-21swapper/319:25:373
2343599170,15cyclictest0-21swapper/319:25:373
2343499170,17cyclictest0-21swapper/223:03:402
2343499170,17cyclictest0-21swapper/223:03:402
2343399173,14cyclictest0-21swapper/100:04:541
2343399173,14cyclictest0-21swapper/100:04:541
2343399172,12cyclictest0-21swapper/123:05:071
2343299172,15cyclictest0-21swapper/022:40:030
2343999162,14cyclictest0-21swapper/723:25:387
2343999160,16cyclictest0-21swapper/719:22:347
2343999160,15cyclictest0-21swapper/722:43:517
2343999160,15cyclictest0-21swapper/720:09:237
2343999160,14cyclictest0-21swapper/719:31:107
2343999160,14cyclictest0-21swapper/719:31:107
2343999160,13cyclictest0-21swapper/719:15:407
2343899160,16cyclictest0-21swapper/619:37:016
2343799160,16cyclictest0-21swapper/522:27:515
2343799160,14cyclictest0-21swapper/521:09:315
2343699162,14cyclictest0-21swapper/423:05:524
2343699162,14cyclictest0-21swapper/420:49:304
2343699162,14cyclictest0-21swapper/420:49:304
23436991616,0cyclictest0-21swapper/421:02:274
23436991616,0cyclictest0-21swapper/421:02:274
2343699160,16cyclictest0-21swapper/422:11:594
2343699160,16cyclictest0-21swapper/419:26:344
2343699160,16cyclictest0-21swapper/419:26:344
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional