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2021-01-20 - 13:32

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.19.25-rt16 (Profile)

Latency plot of system in rack #3, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot0.osadl.org (updated Wed Jan 20, 2021 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158232510,2sleep32608499cyclictest10:13:023
158232510,2sleep32608499cyclictest10:13:023
2574125025,9sleep70-21swapper/707:04:337
2574125025,9sleep70-21swapper/707:04:337
84512420,1sleep1775-21runrttasks07:32:451
84512420,1sleep1775-21runrttasks07:32:451
2569624230,8sleep20-21swapper/207:03:562
2569624230,8sleep20-21swapper/207:03:562
2568824229,9sleep30-21swapper/307:03:493
2568824229,9sleep30-21swapper/307:03:493
2574824027,9sleep50-21swapper/507:04:395
2574824027,9sleep50-21swapper/507:04:395
2568524027,9sleep00-21swapper/007:03:460
2568524027,9sleep00-21swapper/007:03:460
2568923926,9sleep40-21swapper/407:03:504
2568923926,9sleep40-21swapper/407:03:504
2568223926,9sleep60-21swapper/607:03:446
2568223926,9sleep60-21swapper/607:03:446
2574423827,8sleep10-21swapper/107:04:351
2574423827,8sleep10-21swapper/107:04:351
26085991714,1cyclictest1175-21nfsd12:27:084
26085991714,1cyclictest1175-21nfsd12:27:084
26082991612,4cyclictest25-21ksoftirqd/112:28:441
26082991612,4cyclictest25-21ksoftirqd/112:28:441
26082991612,4cyclictest25-21ksoftirqd/112:28:441
2608899156,6cyclictest26341-21kworker/7:111:47:287
2608899156,6cyclictest26341-21kworker/7:111:47:287
2608899156,4cyclictest6465-21kworker/7:212:02:517
2608899156,4cyclictest6465-21kworker/7:212:02:517
26082991512,1cyclictest25-21ksoftirqd/112:19:181
26082991512,1cyclictest25-21ksoftirqd/112:19:181
2608899149,2cyclictest6826-21kworker/7:009:44:587
2608899149,2cyclictest25892-21kworker/7:207:14:167
2608899149,2cyclictest2181-21kworker/7:209:36:007
2608899149,2cyclictest2181-21kworker/7:209:36:007
2608899146,8cyclictest4108-21kworker/7:210:57:067
2608899146,8cyclictest4108-21kworker/7:210:57:067
2608899146,3cyclictest12552-21kworker/7:412:18:567
2608899146,3cyclictest12552-21kworker/7:412:18:567
2608899146,2cyclictest6826-21kworker/7:009:53:327
2608899146,2cyclictest6826-21kworker/7:009:53:327
2608899146,2cyclictest31536-21kworker/7:208:23:227
2608899146,2cyclictest25706-21kworker/7:108:15:447
2608899143,6cyclictest24745-21kworker/7:209:49:247
2608499149,5cyclictest25657-21kworker/3:108:24:183
2608499149,1cyclictest8082-21kworker/3:207:39:303
2608499149,1cyclictest8082-21kworker/3:207:39:303
2608499146,6cyclictest6635-21kworker/3:112:18:563
2608499146,6cyclictest6635-21kworker/3:112:18:563
2608499146,6cyclictest15554-21kworker/3:009:56:423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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