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2026-02-12 - 02:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 25 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot5.osadl.org.osadl.org (updated Thu Feb 12, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151151830,0ktimers/0287911sleep19:10:180
2889899474133,0cyclictest2035-21cut19:42:000
288989947230,0cyclictest29683-21latency_hist19:16:390
1514700,0ktimers/093331sleep23:43:040
288989946232,0cyclictest23972-21sendmail21:41:410
288989946130,0cyclictest30858-21chrt19:23:070
525504580,0irq/11-sym53c8x130250irq/15-NE200022:27:090
2889899456122,0cyclictest25627-21latency_hist21:52:050
1514550,0ktimers/037431sleep23:06:580
1514550,0ktimers/0167091sleep00:33:170
1514540,0ktimers/0225591sleep21:29:320
1514500,0ktimers/0177691sleep00:41:080
288989944937,0cyclictest19972-21chrt21:12:390
288989944933,0cyclictest11121-21ssh23:56:030
288989944927,0cyclictest14686-21sed20:46:510
525504470,0irq/11-sym53c8x130250irq/15-NE200020:17:440
1514440,0ktimers/088921sleep23:39:530
288989944231,0cyclictest13376-21wc00:11:550
2889899441108,0cyclictest31038-21ls22:31:590
1514390,0ktimers/0117191sleep00:01:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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