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2025-07-02 - 07:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Wed Jul 02, 2025 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
146472205189,11sleep10-21swapper/119:07:351
146242193175,13sleep30-21swapper/319:07:173
147472191174,12sleep20-21swapper/219:08:542
146162185169,11sleep00-21swapper/019:07:100
99892480,0sleep10-21swapper/123:52:281
127382480,0sleep20-21swapper/222:32:062
241692470,0sleep10-21swapper/123:26:411
76692450,0sleep10-21swapper/123:18:451
251282450,0sleep00-21swapper/000:00:160
150972110,1sleep315099-21rt-features22:00:203
27004290,0sleep30-21swapper/320:35:203
150039980,8cyclictest0-21swapper/021:16:270
150039970,7cyclictest0-21swapper/021:36:260
150039970,2cyclictest5220-21ssh21:23:070
150039970,1cyclictest7522-21ssh23:35:130
25766260,0sleep10-21swapper/122:22:201
150039960,6cyclictest19985-21sh00:14:230
150039960,6cyclictest0-21swapper/023:59:540
150039960,6cyclictest0-21swapper/023:44:010
150039960,6cyclictest0-21swapper/021:52:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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