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2022-07-04 - 05:24

x86 Intel Core i5-6440EQ @2700 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #5, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Mon Jul 04, 2022 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7282224208,11sleep10-21swapper/119:08:571
5082222206,11sleep00-21swapper/019:06:110
7412184166,13sleep30-21swapper/319:09:073
6652123110,10sleep20-21swapper/219:08:092
87802530,0sleep00-21swapper/000:17:340
59312470,0sleep25933-21gltestperf23:15:192
183052460,0sleep30-21swapper/321:42:363
277742140,0sleep10-21swapper/122:08:401
196842140,0sleep00-21swapper/023:44:220
72922120,0sleep10-21swapper/123:55:451
242652120,0sleep10-21swapper/123:06:081
75282100,0sleep30-21swapper/322:55:343
145192100,0sleep10-21swapper/121:20:161
103592100,0sleep10-21swapper/119:25:121
30763290,0sleep10-21swapper/100:10:311
1717290,0sleep10-21swapper/122:12:111
10129983,4cyclictest27586-21munin-run00:30:000
10329960,6cyclictest0-21swapper/322:41:203
10329960,5cyclictest0-21swapper/323:40:113
10129960,3cyclictest4639-21latency_hist21:15:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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