You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2022-08-19 - 12:36

x86 Intel Core i5-6440EQ @2700 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #5, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100, highest latencies:
System rack5slot2.osadl.org (updated Fri Aug 19, 2022 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14782225209,11sleep10-21swapper/119:08:241
14872198182,12sleep00-21swapper/019:08:320
14312192160,13sleep30-21swapper/319:07:503
15662167150,13sleep20-21swapper/219:09:342
93012490,0sleep10-21swapper/122:55:001
286312460,0sleep30-21swapper/323:45:233
200932460,0sleep20-21swapper/223:00:302
176472460,0sleep017649-21aten2_r5power_v19:40:140
289212450,0sleep30-21swapper/321:48:083
233862390,0sleep00-21swapper/022:24:010
187682110,0sleep30-21swapper/300:38:593
303622100,0sleep10-21swapper/123:26:421
10392100,1sleep1211ktimersoftd/121:50:231
17869991,4cyclictest24765-21munin-run21:00:000
14411290,0sleep10-21swapper/100:35:291
17979981,5cyclictest0-21swapper/223:05:132
18039975,1cyclictest10567-21ssh21:56:103
18039970,6cyclictest0-21swapper/322:55:133
17979970,7cyclictest0-21swapper/221:00:112
17869971,1cyclictest81rcu_preempt23:15:160
17979960,1cyclictest9416-21cat22:15:172
17869962,2cyclictest3-21ksoftirqd/020:05:180
18039955,0cyclictest26513-21kworker/3:021:21:353
18039955,0cyclictest26513-21kworker/3:020:25:383
18039955,0cyclictest26513-21kworker/3:000:31:543
18039950,5cyclictest0-21swapper/323:59:513
18039950,5cyclictest0-21swapper/319:40:243
18039950,4cyclictest10748-21ssh23:35:143
18039950,4cyclictest10135-21apt-get20:30:113
18039950,4cyclictest0-21swapper/320:45:123
18039950,4cyclictest0-21swapper/319:10:133
17979954,1cyclictest31-21ksoftirqd/200:35:162
17979954,1cyclictest0-21swapper/222:04:572
17979952,3cyclictest740-21snmpd22:49:422
17979950,5cyclictest0-21swapper/222:25:192
17919951,2cyclictest0-21swapper/123:10:141
17919951,2cyclictest0-21swapper/121:05:111
17919950,5cyclictest0-21swapper/121:21:571
17869955,0cyclictest0-21swapper/023:50:400
17869955,0cyclictest0-21swapper/000:38:320
17869953,0cyclictest3-21ksoftirqd/023:40:160
17869953,0cyclictest3-21ksoftirqd/022:30:120
17869953,0cyclictest3-21ksoftirqd/020:40:170
17869953,0cyclictest3-21ksoftirqd/019:50:130
17869952,2cyclictest3-21ksoftirqd/021:25:060
17869952,1cyclictest0-21swapper/022:00:130
17869952,0cyclictest81rcu_preempt23:35:500
17869951,1cyclictest3-21ksoftirqd/023:45:160
17869951,1cyclictest3-21ksoftirqd/023:20:140
17869951,1cyclictest3-21ksoftirqd/020:45:130
17869951,1cyclictest3-21ksoftirqd/019:30:210
17869951,1cyclictest3-21ksoftirqd/000:05:230
17869951,0cyclictest81rcu_preempt23:02:520
17869951,0cyclictest81rcu_preempt22:05:170
17869951,0cyclictest81rcu_preempt22:05:160
17869951,0cyclictest3-21ksoftirqd/023:10:150
17869950,5cyclictest0-21swapper/000:17:260
17869950,1cyclictest81rcu_preempt22:10:140
17869950,1cyclictest81rcu_preempt00:30:120
17869950,1cyclictest3-21ksoftirqd/023:55:220
17869950,1cyclictest3-21ksoftirqd/023:25:220
17869950,1cyclictest3-21ksoftirqd/022:45:240
17869950,1cyclictest3-21ksoftirqd/022:35:110
17869950,1cyclictest3-21ksoftirqd/000:30:000
17869950,1cyclictest0-21swapper/021:35:130
17869950,1cyclictest0-21swapper/021:15:140
17869950,1cyclictest0-21swapper/020:50:190
17869950,1cyclictest0-21swapper/000:20:160
17869950,0cyclictest81rcu_preempt21:30:220
17869950,0cyclictest0-21swapper/021:45:220
18039944,0cyclictest0-21swapper/323:11:063
18039944,0cyclictest0-21swapper/322:02:093
18039944,0cyclictest0-21swapper/300:20:143
18039942,2cyclictest26513-21kworker/3:021:05:003
18039941,3cyclictest740-21snmpd21:51:453
18039941,2cyclictest0-21swapper/322:50:133
18039940,4cyclictest62950irq/126-eth1-Tx23:50:163
18039940,4cyclictest23345-21hddtemp_smartct20:55:163
18039940,4cyclictest0-21swapper/323:40:143
18039940,4cyclictest0-21swapper/323:30:133
18039940,4cyclictest0-21swapper/323:15:133
18039940,4cyclictest0-21swapper/322:45:143
18039940,4cyclictest0-21swapper/322:30:123
18039940,4cyclictest0-21swapper/322:15:113
18039940,4cyclictest0-21swapper/322:13:313
18039940,4cyclictest0-21swapper/322:05:393
18039940,4cyclictest0-21swapper/322:05:383
18039940,4cyclictest0-21swapper/321:38:443
18039940,4cyclictest0-21swapper/321:15:153
18039940,4cyclictest0-21swapper/320:50:123
18039940,4cyclictest0-21swapper/320:20:193
18039940,4cyclictest0-21swapper/319:55:113
18039940,4cyclictest0-21swapper/319:45:123
18039940,4cyclictest0-21swapper/300:05:153
18039940,4cyclictest0-21swapper/300:00:133
18039940,3cyclictest8164-21df19:20:153
18039940,3cyclictest548-21users21:30:213
18039940,3cyclictest30188-21/usr/sbin/munin21:10:213
18039940,3cyclictest29713-21diskmemload23:20:463
18039940,3cyclictest29713-21diskmemload22:40:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional