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2023-01-28 - 11:03

x86 Intel Core i5-6440EQ @2700 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #5, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot2.osadl.org (updated Fri Jan 27, 2023 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28982216201,11sleep10-21swapper/107:08:291
27912195178,12sleep30-21swapper/307:07:053
27532172156,11sleep00-21swapper/007:06:350
2718210992,12sleep20-21swapper/207:06:092
261692510,0sleep30-21swapper/312:23:543
72602450,0sleep10-21swapper/109:34:401
133582150,0sleep00-21swapper/010:17:160
293772130,0sleep00-21swapper/012:05:300
90242100,0sleep10-21swapper/107:20:011
161062100,0sleep10-21swapper/110:39:111
31709982,3cyclictest19691-21perf12:39:590
31899970,6cyclictest0-21swapper/308:05:183
31759970,7cyclictest0-21swapper/112:30:101
31709971,3cyclictest1631-21munin-run11:10:010
31899960,5cyclictest0-21swapper/308:30:143
31899955,0cyclictest6375-21kworker/3:112:25:393
31899955,0cyclictest6375-21kworker/3:109:37:433
31899955,0cyclictest0-21swapper/311:39:233
31899953,1cyclictest16392-21ssh09:40:143
31899950,5cyclictest0-21swapper/312:08:553
31899950,5cyclictest0-21swapper/309:46:283
31899950,4cyclictest3772-21apt-get12:30:113
31899950,4cyclictest29163-21ssh10:07:063
31899950,4cyclictest0-21swapper/311:50:113
31849955,0cyclictest0-21swapper/209:55:142
31849950,5cyclictest0-21swapper/212:06:462
31849950,5cyclictest0-21swapper/211:39:342
31849950,5cyclictest0-21swapper/209:27:012
31849950,4cyclictest0-21swapper/207:55:142
31849950,0cyclictest0-21swapper/211:00:592
31759950,5cyclictest0-21swapper/111:25:261
31759950,5cyclictest0-21swapper/109:21:021
31709950,5cyclictest0-21swapper/011:20:230
31709950,5cyclictest0-21swapper/009:30:250
31709950,5cyclictest0-21swapper/009:20:130
31709950,4cyclictest0-21swapper/007:10:130
9598240,0sleep20-21swapper/207:20:172
31899944,0cyclictest6375-21kworker/3:109:26:353
31899944,0cyclictest6375-21kworker/3:107:45:473
31899944,0cyclictest0-21swapper/310:15:433
31899944,0cyclictest0-21swapper/307:12:303
31899943,1cyclictest0-21swapper/308:40:063
31899941,2cyclictest0-21swapper/308:15:163
31899940,4cyclictest0-21swapper/311:55:343
31899940,4cyclictest0-21swapper/311:45:103
31899940,4cyclictest0-21swapper/311:20:113
31899940,4cyclictest0-21swapper/310:55:163
31899940,4cyclictest0-21swapper/310:54:133
31899940,4cyclictest0-21swapper/310:45:153
31899940,4cyclictest0-21swapper/310:31:283
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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