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2026-01-25 - 13:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot2.osadl.org (updated Sun Jan 25, 2026 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
229352193176,12sleep30-21swapper/319:07:093
230352187171,11sleep10-21swapper/119:08:281
228312182166,11sleep00-21swapper/019:05:500
228112173156,12sleep20-21swapper/219:05:372
65782480,0sleep20-21swapper/223:08:332
139902460,0sleep00-21swapper/022:25:110
197072440,0sleep10-21swapper/123:30:171
74012120,0sleep10-21swapper/122:53:061
290752120,0sleep30-21swapper/323:03:453
127352120,0sleep10-21swapper/122:08:551
97212110,0sleep10-21swapper/122:38:371
10889270,0sleep20-21swapper/223:25:552
233419960,6cyclictest0-21swapper/323:19:543
233359961,3cyclictest0-21swapper/122:00:101
233359961,3cyclictest0-21swapper/121:40:121
233319960,6cyclictest0-21swapper/023:50:160
233319960,3cyclictest27848-21munin-run23:35:000
9265250,0sleep29261-21ntp_states21:20:152
233419950,5cyclictest11109-21apt-get22:55:133
233419950,5cyclictest0-21swapper/323:29:393
233419950,5cyclictest0-21swapper/322:50:123
233419950,5cyclictest0-21swapper/322:38:003
233419950,5cyclictest0-21swapper/300:37:273
233419950,5cyclictest0-21swapper/300:27:333
233419950,4cyclictest0-21swapper/323:40:113
233379953,2cyclictest0-21swapper/200:12:192
233379953,1cyclictest2260-21ssh22:35:122
233379951,2cyclictest0-21swapper/223:30:112
233379950,5cyclictest3691-21perf20:40:002
233379950,5cyclictest0-21swapper/222:00:482
233379950,5cyclictest0-21swapper/221:14:222
233379950,5cyclictest0-21swapper/221:14:212
233379950,5cyclictest0-21swapper/200:27:272
233379950,4cyclictest0-21swapper/220:05:122
233379950,0cyclictest18731-21diskmemload22:24:132
233359952,2cyclictest0-21swapper/123:15:111
233359951,2cyclictest0-21swapper/123:20:111
233359951,2cyclictest0-21swapper/122:40:121
233359951,2cyclictest0-21swapper/122:10:131
233359951,2cyclictest0-21swapper/121:50:111
233359951,2cyclictest0-21swapper/120:10:111
233359951,2cyclictest0-21swapper/100:25:131
233359951,1cyclictest0-21swapper/121:10:111
233359951,1cyclictest0-21swapper/121:10:111
233359950,5cyclictest0-21swapper/122:56:421
233359950,0cyclictest0-21swapper/123:25:131
233319950,5cyclictest0-21swapper/000:25:410
233319950,5cyclictest0-21swapper/000:14:220
233319950,4cyclictest26256-21irqstats00:05:160
233319950,4cyclictest0-21swapper/023:29:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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