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2023-12-11 - 01:25

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4s.osadl.org (updated Sun Dec 10, 2023 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1352199193187,2cyclictest27987-21smartctl07:20:251
1352499173171,1cyclictest0-21swapper/207:20:252
1351799124113,10cyclictest0-21swapper/007:20:260
127182118104,10sleep20-21swapper/207:05:392
80132117104,9sleep30-21swapper/307:05:183
131122116103,10sleep00-21swapper/007:07:050
131432115102,10sleep10-21swapper/107:07:301
1352199109104,2cyclictest0-21swapper/107:10:031
13524999490,3cyclictest15706-21kworker/u16:3+events_unbound10:55:272
13521999390,2cyclictest15706-21kworker/u16:3+events_unbound10:15:361
13524999285,5cyclictest26033-21kworker/u16:0+events_unbound08:00:312
13521999289,2cyclictest15706-21kworker/u16:3+events_unbound07:50:021
13524999088,1cyclictest0-21swapper/207:10:022
13521998481,2cyclictest26033-21kworker/u16:0+events_unbound08:30:221
13524997773,3cyclictest15706-21kworker/u16:3+events_unbound07:50:032
13521996763,3cyclictest15706-21kworker/u16:3+events_unbound08:45:361
13521996662,3cyclictest26033-21kworker/u16:0+events_unbound12:35:381
13521996445,12cyclictest26033-21kworker/u16:0+events_unbound11:59:261
13521996359,3cyclictest26033-21kworker/u16:0+events_unbound09:35:371
13524996258,3cyclictest15706-21kworker/u16:3+events_unbound08:25:372
13521996258,3cyclictest15706-21kworker/u16:3+events_unbound12:10:361
13521996157,3cyclictest15706-21kworker/u16:3+events_unbound09:30:361
13517996157,3cyclictest15706-21kworker/u16:3+events_unbound07:39:560
13521995955,3cyclictest15706-21kworker/u16:3+events_unbound11:15:351
13524995853,3cyclictest26033-21kworker/u16:0+events_unbound09:50:302
13521995854,3cyclictest15706-21kworker/u16:3+events_unbound11:50:341
13521995751,3cyclictest15706-21kworker/u16:3+events_unbound07:30:431
13521995652,3cyclictest15706-21kworker/u16:3+events_unbound09:20:331
13521995652,3cyclictest15706-21kworker/u16:3+events_unbound07:45:401
13521995551,3cyclictest26033-21kworker/u16:0+events_unbound10:30:341
13521995551,3cyclictest26033-21kworker/u16:0+events_unbound08:05:321
13524995334,12cyclictest15706-21kworker/u16:3+events_unbound11:55:112
13524995247,3cyclictest15706-21kworker/u16:3+events_unbound07:40:392
13524995229,15cyclictest15706-21kworker/u16:3+events_unbound10:42:392
13521995248,3cyclictest26033-21kworker/u16:0+events_unbound11:45:311
13524995147,3cyclictest15706-21kworker/u16:3+events_unbound10:10:312
13524995046,3cyclictest15706-21kworker/u16:3+events_unbound12:25:212
13524995046,3cyclictest15706-21kworker/u16:3+events_unbound09:10:352
13521995046,3cyclictest15706-21kworker/u16:3+events_unbound09:25:261
13521995044,2cyclictest15706-21kworker/u16:3+events_unbound10:00:011
13524994945,3cyclictest15706-21kworker/u16:3+events_unbound10:50:332
13524994945,3cyclictest15706-21kworker/u16:3+events_unbound07:25:302
13521994945,3cyclictest26033-21kworker/u16:0+events_unbound11:30:351
13521994945,3cyclictest15706-21kworker/u16:3+events_unbound07:55:061
13521994931,15cyclictest26033-21kworker/u16:0+events_unbound10:49:451
13521994844,3cyclictest26033-21kworker/u16:0+events_unbound07:25:391
13521994843,3cyclictest15706-21kworker/u16:3+events_unbound12:15:231
13524994743,3cyclictest15706-21kworker/u16:3+events_unbound11:45:092
13524994743,3cyclictest15706-21kworker/u16:3+events_unbound10:45:232
13524994742,4cyclictest26033-21kworker/u16:0+events_unbound08:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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