OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8
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Click here to display the system's profile data or here to proceed to next system.

Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.
Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system

Characteristics of the 50 highest latencies:

System rack5slot4s.osadl.org (updated Fri Jul 04, 2025 12:44:38)
Delayed (victim)					Switcher (culprit)			Timestamp	CPU
PID	Prio	Total latency (µs)	T^(,W^*) latency (µs)	Cmd	PID	Prio	Cmd	Timestamp	CPU
7457	99	182	179,1	cyclictest	0	-21	swapper/1	07:14:18	1
7455	99	161	151,9	cyclictest	0	-21	swapper/0	07:10:00	0
2096	2	119	94,10	sleep2	0	-21	swapper/2	07:05:11	2
7460	99	115	113,1	cyclictest	0	-21	swapper/2	07:10:00	2
2190	2	115	102,9	sleep3	0	-21	swapper/3	07:05:17	3
6936	2	109	96,10	sleep1	0	-21	swapper/1	07:06:06	1
7042	2	107	95,9	sleep0	0	-21	swapper/0	07:07:29	0
7460	99	57	53,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	08:40:02	2
7460	99	52	47,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	10:45:02	2
7460	99	47	42,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	08:45:26	2
7457	99	45	39,5	cyclictest	20810	-21	kworker/u16:2+events_unbound	12:15:02	1
7460	99	44	41,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	07:55:32	2
7460	99	43	40,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	12:35:27	2
7460	99	43	39,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	07:30:24	2
7460	99	42	38,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	08:00:16	2
7460	99	42	38,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	10:40:27	2
7460	99	42	38,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	08:50:27	2
7460	99	42	38,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	08:10:29	2
7460	99	42	36,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	07:25:17	2
22344	2	42	0,1	sleep0	18	1	rcuc/0	10:45:21	0
7460	99	40	36,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	09:20:27	2
7460	99	39	36,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	09:45:27	2
7460	99	38	34,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	08:05:26	2
7460	99	38	30,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	11:55:25	2
7460	99	37	34,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	10:00:25	2
7460	99	37	33,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	12:10:20	2
7460	99	37	33,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	09:35:25	2
7460	99	37	33,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	07:15:22	2
7460	99	36	32,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	11:05:27	2
7460	99	36	32,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	08:35:17	2
7460	99	36	32,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	08:20:26	2
7460	99	35	32,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	09:05:17	2
7460	99	35	31,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	12:30:28	2
7460	99	35	28,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	08:55:37	2
7460	99	34	31,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	09:40:16	2
7460	99	34	31,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	07:40:25	2
7460	99	34	30,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	11:00:15	2
7460	99	34	30,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	10:20:27	2
7460	99	34	30,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	07:20:30	2
7460	99	33	30,2	cyclictest	31576	-21	kworker/u16:1+events_unbound	09:00:16	2
7460	99	33	29,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	12:25:27	2
7460	99	33	29,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	11:20:18	2
7460	99	33	29,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	10:15:21	2
7460	99	33	26,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	09:55:24	2
7460	99	33	25,3	cyclictest	20810	-21	kworker/u16:2+events_unbound	11:50:16	2
7460	99	32	29,2	cyclictest	31576	-21	kworker/u16:1+events_unbound	09:15:26	2
7460	99	32	29,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	10:50:24	2
7460	99	32	29,2	cyclictest	20810	-21	kworker/u16:2+events_unbound	10:50:24	2
7460	99	32	28,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	07:35:27	2
7460	99	32	26,3	cyclictest	31576	-21	kworker/u16:1+events_unbound	09:10:15	2
^Timer ^*Wakeup (latency=timer+wakeup+contextswitch)


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This page was last modified on 2019-05-28 - 00:17