OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8
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Click here to display the system's profile data or here to proceed to next system.

Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.
Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system

Characteristics of the 50 highest latencies:

System rack5slot4s.osadl.org (updated Mon Jan 20, 2025 12:44:40)
Delayed (victim)					Switcher (culprit)			Timestamp	CPU
PID	Prio	Total latency (µs)	T^(,W^*) latency (µs)	Cmd	PID	Prio	Cmd	Timestamp	CPU
18152	2	121	109,7	sleep3	0	-21	swapper/3	07:05:27	3
18517	2	117	104,9	sleep2	0	-21	swapper/2	07:06:46	2
18429	2	115	91,10	sleep1	0	-21	swapper/1	07:05:37	1
18942	99	108	100,7	cyclictest	0	-21	swapper/0	07:13:04	0
13589	2	106	94,9	sleep0	0	-21	swapper/0	07:05:04	0
18947	99	102	98,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	08:20:26	1
18947	99	88	84,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	08:40:01	1
18947	99	80	74,4	cyclictest	22210	-21	kworker/u16:1+events_unbound	11:50:21	1
18947	99	71	65,4	cyclictest	11402	-21	kworker/u16:2+events_unbound	07:40:17	1
18947	99	71	55,11	cyclictest	29653	-21	kworker/u16:3+events_unbound	08:50:18	1
18947	99	69	65,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	11:30:21	1
18947	99	69	65,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	11:30:21	1
18947	99	69	64,4	cyclictest	11402	-21	kworker/u16:2+events_unbound	09:30:20	1
18947	99	69	63,5	cyclictest	11402	-21	kworker/u16:2+events_unbound	09:40:24	1
18947	99	64	60,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	12:00:25	1
18947	99	64	60,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	07:15:26	1
18947	99	64	60,3	cyclictest	22210	-21	kworker/u16:1+events_unbound	11:20:25	1
18947	99	64	60,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	09:00:24	1
18947	99	63	59,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	11:15:28	1
18947	99	62	58,3	cyclictest	22210	-21	kworker/u16:1+events_unbound	11:10:20	1
18947	99	61	56,3	cyclictest	22210	-21	kworker/u16:1+events_unbound	11:55:14	1
18947	99	60	56,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	10:20:24	1
18947	99	59	55,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	12:15:26	1
18947	99	59	55,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	07:25:24	1
18947	99	59	54,3	cyclictest	22210	-21	kworker/u16:1+events_unbound	11:00:12	1
18947	99	58	54,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	07:45:24	1
18947	99	57	53,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	12:30:21	1
18947	99	57	53,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	12:20:24	1
18947	99	57	53,3	cyclictest	22210	-21	kworker/u16:1+events_unbound	10:30:20	1
18947	99	57	53,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	09:50:20	1
18947	99	57	45,9	cyclictest	29653	-21	kworker/u16:3+events_unbound	12:35:02	1
18947	99	56	53,2	cyclictest	22210	-21	kworker/u16:1+events_unbound	10:10:10	1
18947	99	56	52,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	07:20:29	1
18947	99	56	52,3	cyclictest	22210	-21	kworker/u16:1+events_unbound	10:15:27	1
18947	99	54	50,3	cyclictest	22210	-21	kworker/u16:1+events_unbound	11:40:26	1
18947	99	54	50,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	08:10:12	1
18947	99	51	47,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	10:00:18	1
18947	99	50	45,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	09:35:19	1
18947	99	49	45,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	08:25:29	1
18947	99	49	45,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	08:30:26	1
18947	99	48	44,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	10:35:19	1
18947	99	48	44,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	09:55:17	1
18947	99	48	44,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	07:35:18	1
18947	99	46	42,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	07:50:30	1
18947	99	46	41,4	cyclictest	22210	-21	kworker/u16:1+events_unbound	11:00:00	1
18947	99	45	41,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	09:15:25	1
18947	99	42	38,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	10:40:14	1
18947	99	40	36,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	11:35:30	1
18947	99	40	36,3	cyclictest	11402	-21	kworker/u16:2+events_unbound	09:20:14	1
18947	99	39	35,3	cyclictest	29653	-21	kworker/u16:3+events_unbound	08:15:14	1
^Timer ^*Wakeup (latency=timer+wakeup+contextswitch)


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This page was last modified on 2019-05-28 - 00:17