OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8
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Click here to display the system's profile data or here to proceed to next system.

Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.
Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system

Characteristics of the 50 highest latencies:

System rack5slot4s.osadl.org (updated Thu Sep 19, 2024 12:44:39)
Delayed (victim)					Switcher (culprit)			Timestamp	CPU
PID	Prio	Total latency (µs)	T^(,W^*) latency (µs)	Cmd	PID	Prio	Cmd	Timestamp	CPU
30093	99	176	171,2	cyclictest	0	-21	swapper/1	07:10:01	1
30093	99	171	168,2	cyclictest	10091	-21	strings	07:15:21	1
29730	2	117	94,9	sleep0	0	-21	swapper/0	07:08:17	0
29816	2	116	103,10	sleep2	0	-21	swapper/2	07:09:24	2
29564	2	115	101,10	sleep3	0	-21	swapper/3	07:06:08	3
29711	2	107	94,10	sleep1	0	-21	swapper/1	07:08:02	1
30088	99	90	80,9	cyclictest	30445	-21	gpgv	07:10:01	0
30088	99	86	77,9	cyclictest	0	-21	swapper/0	07:15:21	0
30096	99	80	78,1	cyclictest	0	-21	swapper/2	07:10:01	2
30096	99	77	75,1	cyclictest	0	-21	swapper/2	07:15:21	2
30088	99	69	64,4	cyclictest	3561	-21	kworker/u16:2+events_unbound	08:45:25	0
30096	99	52	47,3	cyclictest	28783	-21	kworker/u16:0+events_unbound	08:35:19	2
30096	99	46	41,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	08:40:20	2
30096	99	42	38,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	11:15:20	2
30096	99	42	35,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	10:30:25	2
30088	99	41	36,4	cyclictest	29894	-21	kworker/u16:3+events_unbound	10:55:13	0
30088	99	41	35,4	cyclictest	29894	-21	kworker/u16:3+events_unbound	07:40:20	0
30096	99	40	36,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	07:45:02	2
30096	99	39	36,2	cyclictest	29894	-21	kworker/u16:3+events_unbound	09:15:35	2
30096	99	39	35,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	08:05:25	2
30096	99	39	35,3	cyclictest	29894	-21	kworker/u16:3+events_unbound	09:25:27	2
30088	99	39	35,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	07:30:17	0
30088	99	38	34,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	12:20:03	0
30088	99	38	34,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	10:40:25	0
30096	99	37	33,3	cyclictest	4054	-21	kworker/u16:0+events_unbound	07:20:24	2
30096	99	37	33,3	cyclictest	29894	-21	kworker/u16:3+events_unbound	12:05:22	2
30088	99	37	33,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	09:30:26	0
30088	99	37	33,3	cyclictest	29894	-21	kworker/u16:3+events_unbound	07:25:27	0
30096	99	36	32,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	12:25:24	2
30096	99	35	31,2	cyclictest	29894	-21	kworker/u16:3+events_unbound	10:25:26	2
30096	99	34	30,3	cyclictest	29894	-21	kworker/u16:3+events_unbound	09:40:02	2
30096	99	34	30,3	cyclictest	28783	-21	kworker/u16:0+events_unbound	09:05:19	2
30088	99	34	30,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	07:50:20	0
30096	99	33	30,2	cyclictest	3561	-21	kworker/u16:2+events_unbound	09:55:25	2
30096	99	33	29,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	07:35:14	2
30088	99	33	30,2	cyclictest	29894	-21	kworker/u16:3+events_unbound	11:20:13	0
30088	99	33	29,3	cyclictest	24032	-21	kworker/u16:1+events_unbound	12:35:18	0
30088	99	33	28,4	cyclictest	28783	-21	kworker/u16:0+events_unbound	08:35:13	0
30096	99	32	28,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	10:05:25	2
30096	99	32	28,3	cyclictest	29894	-21	kworker/u16:3+events_unbound	09:50:26	2
30096	99	31	28,2	cyclictest	29894	-21	kworker/u16:3+events_unbound	12:15:20	2
30096	99	31	28,2	cyclictest	29894	-21	kworker/u16:3+events_unbound	08:25:15	2
30096	99	31	28,2	cyclictest	29894	-21	kworker/u16:3+events_unbound	07:40:01	2
30096	99	31	27,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	09:00:14	2
30096	99	31	27,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	07:30:24	2
30088	99	31	27,3	cyclictest	29894	-21	kworker/u16:3+events_unbound	11:45:26	0
30096	99	30	27,2	cyclictest	3561	-21	kworker/u16:2+events_unbound	11:30:21	2
30096	99	30	27,2	cyclictest	3561	-21	kworker/u16:2+events_unbound	09:45:25	2
30096	99	30	26,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	11:50:03	2
30096	99	30	26,3	cyclictest	3561	-21	kworker/u16:2+events_unbound	10:50:29	2
^Timer ^*Wakeup (latency=timer+wakeup+contextswitch)


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This page was last modified on 2019-05-28 - 00:17