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2022-01-23 - 19:49

Intel(R) Celeron(R) CPU N3350 @ 1.10GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26436 SMIs that occured during the measurement.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot4.osadl.org (updated Sun Jan 23, 2022 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2145899334331,2cyclictest11860-21kworker/0:110:16:000
2145899333330,2cyclictest20197-21kworker/0:012:34:310
2145899328325,2cyclictest25398-21kworker/0:011:27:030
2145899326323,2cyclictest31832-21kworker/0:210:01:100
2145899325321,2cyclictest25398-21kworker/0:011:12:010
2145899324321,2cyclictest28556-21kworker/0:209:23:450
2145899323320,2cyclictest31832-21kworker/0:209:58:090
2145899323319,2cyclictest32702-21kworker/0:112:37:140
2145899322320,1cyclictest31748-21kworker/0:011:52:270
2145899322319,2cyclictest28556-21kworker/0:209:14:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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