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2023-12-08 - 04:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 25958 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot4.osadl.org (updated Thu Nov 30, 2023 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29916993470,345cyclictest0-21swapper/010:45:060
2991699339336,2cyclictest3764-21kworker/0:109:20:090
29916993380,336cyclictest0-21swapper/012:22:220
29916993370,1cyclictest0-21swapper/012:37:000
29916993351,3cyclictest31329-21diskmemload11:29:170
29916993350,1cyclictest0-21swapper/011:42:340
2991699334331,2cyclictest0-21swapper/007:17:550
2991699333331,1cyclictest0-21swapper/007:58:380
2991699331329,1cyclictest0-21swapper/012:15:330
2991699331328,2cyclictest0-21swapper/010:24:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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