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2025-07-03 - 14:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26516 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot4.osadl.org (updated Thu Jul 03, 2025 13:09:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32410:12:056431
331,10:06:416430
"maxima":[6429
010:06:416426
0,10:06:416425
0,10:06:416424
0,10:06:416423
0,10:06:416422
0,10:06:416421
0,10:06:416420
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0,10:06:416409
0,10:06:416408
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0,10:06:416401
0,10:06:416400
0,10:06:416399
0,10:06:416398
0,10:06:416397
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0,10:06:416385
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0,10:06:416380
0,10:06:416379
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0,10:06:416364
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1,10:06:416351
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0,10:06:416349
1,10:06:416348
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1,10:06:416346
0,10:06:416345
1,10:06:416344
2,10:06:416343
1,10:06:416342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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