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2024-04-20 - 16:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26432 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot4.osadl.org (updated Sat Apr 20, 2024 13:13:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32412:47:346431
331,12:42:106430
"maxima":[6429
012:42:106426
0,12:42:106425
0,12:42:106424
0,12:42:106423
0,12:42:106422
0,12:42:106421
0,12:42:106420
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0,12:42:106413
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0,12:42:106410
0,12:42:106409
0,12:42:106408
0,12:42:106407
0,12:42:106406
0,12:42:106405
0,12:42:106404
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0,12:42:106402
0,12:42:106401
0,12:42:106400
0,12:42:106399
0,12:42:106398
0,12:42:106397
0,12:42:106396
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0,12:42:106393
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0,12:42:106389
0,12:42:106388
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0,12:42:106386
0,12:42:106385
0,12:42:106384
0,12:42:106383
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0,12:42:106381
0,12:42:106380
0,12:42:106379
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0,12:42:106373
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0,12:42:106365
0,12:42:106364
0,12:42:106363
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0,12:42:106361
0,12:42:106360
0,12:42:106359
0,12:42:106358
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0,12:42:106356
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0,12:42:106354
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0,12:42:106352
1,12:42:106351
0,12:42:106350
0,12:42:106349
1,12:42:106348
0,12:42:106347
1,12:42:106346
0,12:42:106345
1,12:42:106344
2,12:42:106343
1,12:42:106342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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