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2022-05-17 - 23:54

x86 Intel Celeron N3350 @1100 MHz, Linux 5.15.32-rt39 (Profile)

Latency plot of system in rack #6, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26436 SMIs that occured during the measurement.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot4.osadl.org (updated Tue May 17, 2022 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1648099331329,1cyclictest0-21swapper/023:06:440
1648099330328,1cyclictest0-21swapper/021:13:250
1648099330327,2cyclictest0-21swapper/021:16:570
1648099328325,2cyclictest0-21swapper/022:30:370
1648099328324,2cyclictest18863-21df22:35:120
1648099325322,2cyclictest0-21swapper/021:29:150
1648099324321,2cyclictest6973-21kworker/0:120:37:430
1648099324321,2cyclictest0-21swapper/023:52:140
1648099322320,1cyclictest0-21swapper/021:43:120
1648099322319,2cyclictest0-21swapper/022:46:500
1648099321318,2cyclictest0-21swapper/022:10:290
1648099320317,2cyclictest0-21swapper/023:03:340
1648099319316,2cyclictest0-21swapper/021:35:360
16480993190,316cyclictest22028-21ssh00:05:090
1648099318316,1cyclictest0-21swapper/023:41:190
1648099318315,2cyclictest0-21swapper/021:56:450
1648099317314,2cyclictest27189-21kworker/0:222:45:010
1648099316313,2cyclictest16038-21kworker/0:119:30:020
1648099316313,2cyclictest0-21swapper/022:55:480
1648099316310,4cyclictest20032-21sh23:19:480
16480993150,313cyclictest0-21swapper/022:08:310
1648099314312,1cyclictest0-21swapper/022:51:550
1648099314312,1cyclictest0-21swapper/000:27:140
1648099314312,1cyclictest0-21swapper/000:10:230
1648099314311,2cyclictest6973-21kworker/0:120:30:230
1648099313311,1cyclictest0-21swapper/023:33:350
1648099313310,2cyclictest0-21swapper/023:35:130
1648099313310,2cyclictest0-21swapper/023:35:120
1648099313306,6cyclictest0-21swapper/021:54:240
1648099312309,2cyclictest6973-21kworker/0:120:40:110
1648099312308,3cyclictest16038-21kworker/0:119:43:240
1648099311309,1cyclictest0-21swapper/023:58:300
1648099309307,1cyclictest0-21swapper/021:46:360
1648099309306,2cyclictest0-21swapper/022:00:440
1648099309306,2cyclictest0-21swapper/000:16:080
16480993090,1cyclictest0-21swapper/000:03:410
1648099308306,1cyclictest0-21swapper/023:21:180
1648099308305,2cyclictest2167-21ntpq20:10:150
1648099308305,2cyclictest0-21swapper/000:24:000
16480993080,306cyclictest0-21swapper/022:28:590
1648099307305,1cyclictest0-21swapper/020:58:230
1648099307305,1cyclictest0-21swapper/000:33:340
1648099307304,2cyclictest0-21swapper/019:18:170
1648099307302,3cyclictest9482-21ssh23:48:060
161402307277,21sleep10-21swapper/119:08:191
1648099306304,1cyclictest0-21swapper/019:49:340
1648099306303,2cyclictest0-21swapper/023:12:530
1648099306303,2cyclictest0-21swapper/022:19:420
1648099306303,2cyclictest0-21swapper/021:30:580
1648099306303,2cyclictest0-21swapper/021:09:030
1648099306303,2cyclictest0-21swapper/020:22:310
16480993060,1cyclictest0-21swapper/021:24:360
1648099305303,1cyclictest0-21swapper/000:35:080
1648099305302,2cyclictest0-21swapper/020:03:530
1648099305301,3cyclictest16478-21cyclictest20:16:060
1648099304302,1cyclictest0-21swapper/019:13:170
1648099304301,2cyclictest3053-21kworker/0:020:26:420
1648099303301,1cyclictest0-21swapper/020:49:190
1648099303301,1cyclictest0-21swapper/019:28:320
1648199302297,3cyclictest26592-21kworker/1:323:40:001
1648199302297,3cyclictest26592-21kworker/1:323:40:001
1648099302299,2cyclictest9414-21ssh22:22:270
1648099302299,2cyclictest6973-21kworker/0:120:50:160
1648099302299,2cyclictest0-21swapper/023:27:210
1648099302299,2cyclictest0-21swapper/021:04:310
1648099300296,3cyclictest0-21swapper/019:22:330
1648099299297,1cyclictest0-21swapper/019:37:040
1648099297294,2cyclictest0-21swapper/020:05:140
159622297270,19sleep00-21swapper/019:06:230
1648199296293,2cyclictest23510-21kworker/1:222:20:191
1648099296293,2cyclictest0-21swapper/019:55:140
1648199294291,2cyclictest25151-21kworker/1:120:06:151
1648199294291,2cyclictest23510-21kworker/1:222:14:551
1648099294292,1cyclictest0-21swapper/019:52:280
1648199293289,3cyclictest14682-21kworker/1:023:20:161
1648199291288,2cyclictest27521-21kworker/1:023:05:101
1648199289285,2cyclictest5272-21kworker/1:100:29:081
1648199284281,2cyclictest32073-21kworker/1:021:35:241
1648199283279,3cyclictest27521-21kworker/1:022:54:101
1648199274271,2cyclictest18607-21kworker/1:223:25:341
1648199273271,1cyclictest0-21swapper/122:45:151
1648199271266,3cyclictest13600-21kworker/1:200:39:421
1648199270267,2cyclictest14682-21kworker/1:023:15:101
1648199268265,2cyclictest32639-21latency_hist20:05:001
1648199260258,1cyclictest0-21swapper/121:50:011
1648199258255,2cyclictest9928-21kworker/1:023:50:011
1648199257254,2cyclictest9928-21kworker/1:000:03:221
1648199256253,2cyclictest23510-21kworker/1:222:15:111
1648199256253,2cyclictest23510-21kworker/1:222:09:591
1648199256253,2cyclictest18003-21kworker/1:022:35:391
1648199254251,2cyclictest32073-21kworker/1:021:55:221
1648199253250,2cyclictest32073-21kworker/1:021:49:381
1648199252250,1cyclictest0-21swapper/121:33:541
1648199252250,1cyclictest0-21swapper/120:25:141
1648199252249,2cyclictest14682-21kworker/1:023:15:001
1648199251249,1cyclictest0-21swapper/119:45:001
1648199250247,2cyclictest25538-21kworker/1:200:14:311
1648199250247,2cyclictest23510-21kworker/1:222:27:231
1648199249245,2cyclictest21478-21kworker/1:100:05:111
1648199249243,4cyclictest3045-21latency_hist20:15:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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