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2020-03-29 - 11:57

Intel(R) Celeron(R) CPU N3350 @ 1.10GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26430 SMIs that occured during the measurement.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot4.osadl.org (updated Thu Mar 12, 2020 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3223199336333,2cyclictest0-21swapper/008:27:380
3223199335332,2cyclictest0-21swapper/011:33:570
3223199324321,2cyclictest0-21swapper/009:26:050
3223199324321,2cyclictest0-21swapper/007:26:020
3223199323320,2cyclictest0-21swapper/011:07:000
32231993220,321cyclictest0-21swapper/012:28:540
3223199320317,2cyclictest0-21swapper/009:40:240
3223199319316,2cyclictest0-21swapper/012:13:110
3223199319316,2cyclictest0-21swapper/011:36:480
3223199318315,2cyclictest0-21swapper/011:23:410
3223199318315,2cyclictest0-21swapper/009:10:430
3223199318315,2cyclictest0-21swapper/008:22:310
3223199318315,2cyclictest0-21swapper/008:09:100
32231993180,316cyclictest0-21swapper/010:37:230
3223199317314,2cyclictest6575-21kworker/0:107:40:070
3223199317314,2cyclictest16401-21kworker/0:210:14:490
3223199317314,2cyclictest0-21swapper/009:59:540
3223199317314,2cyclictest0-21swapper/007:23:480
3223199316313,2cyclictest6575-21kworker/0:107:57:220
3223199316313,2cyclictest6575-21kworker/0:107:57:220
3223199316313,2cyclictest0-21swapper/012:30:200
3223199316313,2cyclictest0-21swapper/011:40:290
3223199316313,2cyclictest0-21swapper/007:17:550
3223199316297,13cyclictest0-21swapper/010:55:460
3223199315312,2cyclictest0-21swapper/011:49:050
3223199315312,2cyclictest0-21swapper/011:13:400
3223199315312,2cyclictest0-21swapper/009:16:340
3223199315312,2cyclictest0-21swapper/008:12:500
3223199314311,2cyclictest0-21swapper/011:17:000
3223199314311,2cyclictest0-21swapper/010:33:300
3223199314311,2cyclictest0-21swapper/009:21:160
3223199314311,2cyclictest0-21swapper/007:11:450
3223199314302,4cyclictest0-21swapper/009:46:390
3223199313311,1cyclictest0-21swapper/008:15:080
3223199313311,1cyclictest0-21swapper/007:51:340
3223199313310,2cyclictest0-21swapper/012:38:020
3223199313310,2cyclictest0-21swapper/011:01:160
3223199313310,2cyclictest0-21swapper/010:43:540
3223199313310,2cyclictest0-21swapper/010:08:250
3223199313310,2cyclictest0-21swapper/009:07:040
3223199313310,2cyclictest0-21swapper/008:50:260
3223199313310,2cyclictest0-21swapper/008:42:440
3223199313310,2cyclictest0-21swapper/007:45:590
3223199312310,1cyclictest0-21swapper/012:15:050
3223199312309,2cyclictest0-21swapper/012:20:240
3223199312309,2cyclictest0-21swapper/012:09:240
3223199311308,2cyclictest0-21swapper/011:28:410
3223199311308,2cyclictest0-21swapper/010:02:120
3223199311308,2cyclictest0-21swapper/009:38:370
3223199311308,2cyclictest0-21swapper/008:56:520
3223199310307,2cyclictest0-21swapper/012:01:110
3223199310307,2cyclictest0-21swapper/009:51:500
3223199310307,2cyclictest0-21swapper/009:04:070
3223199309307,1cyclictest6575-21kworker/0:108:39:300
3223199309305,2cyclictest6575-21kworker/0:107:30:120
3223199308306,1cyclictest0-21swapper/010:23:050
3223199308305,2cyclictest0-21swapper/010:48:340
3223199308305,2cyclictest0-21swapper/009:33:580
3223199308305,2cyclictest0-21swapper/008:34:430
3223299307304,2cyclictest3005-21kworker/1:008:55:121
3223199307304,2cyclictest0-21swapper/011:58:020
3223199307304,2cyclictest0-21swapper/010:52:000
3223199306303,2cyclictest0-21swapper/008:45:540
3223199306302,2cyclictest6575-21kworker/0:108:00:140
32231993060,304cyclictest0-21swapper/011:50:430
3223199305302,2cyclictest0-21swapper/010:29:130
3223199305302,2cyclictest0-21swapper/010:19:250
3223199305302,2cyclictest0-21swapper/007:38:010
32232992970,295cyclictest20425-21latency_hist08:10:001
318982297231,20sleep10-21swapper/107:08:151
3223299292289,2cyclictest19738-21kworker/1:209:51:501
3223299291288,2cyclictest991-21kworker/1:207:15:001
3223299290285,3cyclictest14276-21sed07:50:061
3223299289287,1cyclictest7614-21kworker/1:110:51:571
3223299287285,1cyclictest24885-21kworker/1:010:01:551
3223299287284,2cyclictest29633-21kworker/1:211:51:541
3223299286284,1cyclictest0-21swapper/109:20:021
3223299285283,1cyclictest0-21swapper/110:25:001
3223299285283,1cyclictest0-21swapper/108:02:241
3223299285283,1cyclictest0-21swapper/107:40:111
3223299285282,2cyclictest23407-21kworker/1:108:30:031
3223299285282,2cyclictest11840-21kworker/1:007:59:451
3223299285282,2cyclictest11840-21kworker/1:007:59:441
3223299282280,1cyclictest0-21swapper/111:25:281
3223299282279,2cyclictest2493-21kworker/1:112:10:111
3223299281279,1cyclictest2493-21kworker/1:112:22:591
3223299281278,2cyclictest2493-21kworker/1:112:08:281
3223299279277,1cyclictest0-21swapper/111:10:121
3223299279277,1cyclictest0-21swapper/109:00:021
3223299279275,2cyclictest25594-21latency_hist08:25:001
318942279247,20sleep00-21swapper/007:08:120
3223299278275,2cyclictest2493-21kworker/1:112:15:091
3223299277274,2cyclictest0-21swapper/111:40:111
3223299276273,2cyclictest19698-21kworker/1:208:11:541
3223299275273,1cyclictest0-21swapper/111:33:501
3223299275273,1cyclictest0-21swapper/110:32:381
3223299275272,2cyclictest12356-21kworker/1:012:36:321
3223299275271,2cyclictest5499-21ps10:35:121
3223299274272,1cyclictest24885-21kworker/1:010:13:441
3223299274272,1cyclictest13559-21kworker/1:109:30:041
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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