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2022-08-11 - 16:29

x86 Intel Celeron N3350 @1100 MHz, Linux 5.15.32-rt39 (Profile)

Latency plot of system in rack #6, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26460 SMIs that occured during the measurement.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack6slot4.osadl.org (updated Thu Aug 11, 2022 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
951699341336,3cyclictest26927-21kworker/1:109:52:521
951599336333,2cyclictest0-21swapper/011:46:450
951599334332,1cyclictest0-21swapper/009:43:340
951599334331,2cyclictest0-21swapper/010:31:350
9515993340,332cyclictest0-21swapper/011:56:000
9515993340,1cyclictest0-21swapper/009:39:230
951699333328,3cyclictest28136-21kworker/1:210:59:041
951699333328,3cyclictest11306-21kworker/1:111:53:111
951599332329,2cyclictest0-21swapper/007:11:310
9515993310,1cyclictest0-21swapper/007:53:500
9515993300,328cyclictest0-21swapper/011:01:460
951699329324,3cyclictest26927-21kworker/1:110:00:471
951699329324,3cyclictest2143-21kworker/1:110:23:311
951599329322,6cyclictest0-21swapper/010:12:510
951699328323,3cyclictest10504-21kworker/1:111:11:341
951699328323,3cyclictest10504-21kworker/1:111:05:191
951599328326,1cyclictest0-21swapper/010:17:330
951599328325,2cyclictest0-21swapper/008:41:080
951599328325,2cyclictest0-21swapper/007:45:510
951599327325,1cyclictest0-21swapper/008:54:500
951599327325,1cyclictest0-21swapper/007:34:090
951599327324,2cyclictest0-21swapper/009:12:240
951599327324,2cyclictest0-21swapper/008:59:080
951599326323,2cyclictest0-21swapper/011:54:290
951599326323,2cyclictest0-21swapper/011:20:080
951599325322,2cyclictest0-21swapper/012:23:190
951599325322,2cyclictest0-21swapper/012:09:340
951699324318,4cyclictest2143-21kworker/1:110:43:081
951599324322,1cyclictest0-21swapper/012:15:380
951599324321,2cyclictest0-21swapper/012:12:240
951599324321,2cyclictest0-21swapper/011:35:200
9515993240,1cyclictest0-21swapper/010:05:400
951699323317,4cyclictest2143-21kworker/1:110:14:371
951599323321,1cyclictest0-21swapper/011:42:500
951599323321,1cyclictest0-21swapper/007:16:070
951599323320,2cyclictest0-21swapper/010:41:240
951599323320,2cyclictest0-21swapper/010:04:080
951699322316,4cyclictest6189-21kworker/1:210:19:151
951599322319,2cyclictest0-21swapper/009:18:050
951599322319,2cyclictest0-21swapper/007:38:180
951699321316,3cyclictest28136-21kworker/1:211:01:581
951699321315,4cyclictest2143-21kworker/1:110:32:161
951599321319,1cyclictest0-21swapper/008:18:150
951599321318,2cyclictest0-21swapper/012:27:140
951599321318,2cyclictest0-21swapper/009:02:090
951599321314,6cyclictest0-21swapper/009:28:390
951599321314,6cyclictest0-21swapper/008:11:090
951599321314,6cyclictest0-21swapper/007:57:370
951699320315,3cyclictest19175-21kworker/1:011:20:271
951599320317,2cyclictest0-21swapper/010:25:240
951599320317,2cyclictest0-21swapper/009:56:240
951599320317,2cyclictest0-21swapper/009:22:400
951599320317,2cyclictest0-21swapper/008:46:330
951699319313,4cyclictest19568-21kworker/1:009:13:571
951699319312,5cyclictest10821-21kworker/1:209:19:501
951599319317,1cyclictest0-21swapper/008:27:160
951599319316,2cyclictest0-21swapper/009:47:590
951699318313,3cyclictest26927-21kworker/1:109:33:231
951699318313,3cyclictest23843-21kworker/1:211:35:161
951599318315,2cyclictest0-21swapper/012:30:220
951599318315,2cyclictest0-21swapper/011:31:250
951599318315,2cyclictest0-21swapper/011:11:000
951599318314,3cyclictest12-21ksoftirqd/010:21:540
951699317310,4cyclictest29780-21kworker/1:210:08:301
951599317315,1cyclictest0-21swapper/009:54:040
951599317315,1cyclictest0-21swapper/009:09:090
951599317315,1cyclictest0-21swapper/008:03:150
951599317314,2cyclictest0-21swapper/011:09:560
951699316310,4cyclictest5505-21kworker/1:209:39:241
951699316310,4cyclictest1814-21kworker/1:212:23:321
951599316313,2cyclictest0-21swapper/010:38:210
951599316313,2cyclictest0-21swapper/008:22:400
951699315309,4cyclictest6275-21kworker/1:012:32:361
951699315309,4cyclictest26927-21kworker/1:109:45:271
951699315308,5cyclictest7271-21kworker/1:211:48:321
951599315313,1cyclictest0-21swapper/008:06:190
951599315312,2cyclictest0-21swapper/011:27:060
9515993150,313cyclictest0-21swapper/010:51:030
951699314310,3cyclictest15392-21kworker/1:011:56:061
951699314309,3cyclictest3266-21kworker/1:011:43:211
951699314308,4cyclictest26927-21kworker/1:109:58:551
951599314307,6cyclictest0-21swapper/010:57:300
951699313308,3cyclictest28136-21kworker/1:210:51:141
951699313308,3cyclictest2143-21kworker/1:110:29:571
951699313308,3cyclictest10821-21kworker/1:209:24:121
951699313307,5cyclictest15392-21kworker/1:012:07:531
951699313307,4cyclictest15392-21kworker/1:012:14:231
951699313307,4cyclictest10821-21kworker/1:209:25:481
951599313306,6cyclictest0-21swapper/012:04:110
9515993130,310cyclictest2175-21users09:30:300
951699312306,4cyclictest6275-21kworker/1:012:27:541
951699312306,4cyclictest26927-21kworker/1:109:42:451
951699310305,3cyclictest23843-21kworker/1:211:31:471
951699310305,3cyclictest23843-21kworker/1:211:28:491
951699310303,4cyclictest23487-21kworker/1:010:48:161
951599310308,1cyclictest0-21swapper/011:18:200
951599310308,1cyclictest0-21swapper/010:47:460
951599310307,2cyclictest0-21swapper/007:27:220
951699309304,3cyclictest29524-21kworker/1:112:18:291
951699309304,3cyclictest15392-21kworker/1:012:01:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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