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2019-07-16 - 03:08

Intel(R) Celeron(R) CPU N3350 @ 1.10GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26470 SMIs that occured during the measurement.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot4.osadl.org (updated Tue Jul 16, 2019 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3093799330327,2cyclictest26713-21kworker/0:223:46:270
3093799327324,2cyclictest28923-21kworker/0:119:26:080
3093799326323,2cyclictest15097-21kworker/0:221:52:480
3093799326323,2cyclictest13385-21kworker/0:123:05:330
3093799325322,2cyclictest2784-21kworker/0:100:29:370
3093799325322,2cyclictest2130-21kworker/0:019:18:560
3093799325322,2cyclictest15097-21kworker/0:221:38:550
3093799324321,2cyclictest12316-21kworker/0:020:07:090
3093799322319,2cyclictest9994-21kworker/0:121:31:580
3093799321319,1cyclictest15097-21kworker/0:221:45:490
3093799320318,1cyclictest7184-21kworker/0:119:44:290
3093799320317,2cyclictest26713-21kworker/0:223:59:320
3093799320317,2cyclictest25302-21kworker/0:122:03:410
3093799319317,1cyclictest12316-21kworker/0:020:14:410
3093799319316,2cyclictest2784-21kworker/0:100:23:150
3093799319316,2cyclictest21763-21kworker/0:220:38:030
3093799319316,2cyclictest15097-21kworker/0:222:13:260
3093799319316,2cyclictest15097-21kworker/0:221:58:180
3093799319316,2cyclictest1431-21kworker/0:022:47:010
3093799318315,2cyclictest21568-21kworker/0:123:36:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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