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2024-04-28 - 08:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26592 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 376 highest latencies:
System rack6slot4.osadl.org (updated Sun Apr 28, 2024 01:14:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32412:47:346431
331,12:42:106430
"maxima":[6429
012:42:106426
0,12:42:106425
0,12:42:106424
0,12:42:106423
0,12:42:106422
0,12:42:106421
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0,12:42:106364
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1,12:42:106351
0,12:42:106350
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1,12:42:106348
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1,12:42:106346
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1,12:42:106344
2,12:42:106343
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3,12:42:106341
0,12:42:106340
0,12:42:106339
4,12:42:106338
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2,12:42:106336
3,12:42:106335
7,12:42:106334
5,12:42:106333
7,12:42:106332
7,12:42:106331
6,12:42:106330
2,12:42:106329
4,12:42:106328
1,12:42:106327
3,12:42:106326
1,12:42:106325
3,12:42:106324
4,12:42:106323
8,12:42:106322
5,12:42:106321
5,12:42:106320
6,12:42:106319
13,12:42:106318
4,12:42:106317
14,12:42:106316
16,12:42:106315
10,12:42:106314
14,12:42:106313
12,12:42:106312
17,12:42:106311
16,12:42:106310
14,12:42:106309
18,12:42:106308
12,12:42:106307
21,12:42:106306
21,12:42:106305
27,12:42:106304
24,12:42:106303
28,12:42:106302
31,12:42:106301
26,12:42:106300
26,12:42:106299
31,12:42:106298
18,12:42:106297
32,12:42:106296
40,12:42:106295
24,12:42:106294
43,12:42:106293
25,12:42:106292
34,12:42:106291
41,12:42:106290
33,12:42:106289
40,12:42:106288
44,12:42:106287
49,12:42:106286
58,12:42:106285
51,12:42:106284
48,12:42:106283
57,12:42:106282
69,12:42:106281
83,12:42:106280
81,12:42:106279
74,12:42:106278
75,12:42:106277
98,12:42:106276
101,12:42:106275
105,12:42:106274
122,12:42:106273
137,12:42:106272
145,12:42:106271
143,12:42:106270
139,12:42:106269
177,12:42:106268
183,12:42:106267
200,12:42:106266
228,12:42:106265
243,12:42:106264
286,12:42:106263
299,12:42:106262
305,12:42:106261
325,12:42:106260
334,12:42:106259
327,12:42:106258
327,12:42:106257
355,12:42:106256
401,12:42:106255
407,12:42:106254
405,12:42:106253
438,12:42:106252
434,12:42:106251
409,12:42:106250
406,12:42:106249
367,12:42:106248
286,12:42:106247
266,12:42:106246
226,12:42:106245
204,12:42:106244
180,12:42:106243
188,12:42:106242
197,12:42:106241
220,12:42:106240
215,12:42:106239
237,12:42:106238
255,12:42:106237
257,12:42:106236
233,12:42:106235
162,12:42:106234
99,12:42:106233
105,12:42:106232
46,12:42:106231
43,12:42:106230
12,12:42:106229
8,12:42:106228
2,12:42:106227
6,12:42:106226
3,12:42:106225
5,12:42:106224
3,12:42:106223
3,12:42:106222
5,12:42:106221
2,12:42:106220
4,12:42:106219
3,12:42:106218
7,12:42:106217
15,12:42:106216
13,12:42:106215
15,12:42:106214
5,12:42:106213
12,12:42:106212
8,12:42:106211
6,12:42:106210
3,12:42:106209
3,12:42:106208
2,12:42:106207
2,12:42:106206
2,12:42:106205
1,12:42:106204
3,12:42:106203
1,12:42:106202
4,12:42:106201
2,12:42:106200
0,12:42:106199
3,12:42:106198
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3,12:42:106191
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2,12:42:106189
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3,12:42:106175
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3,12:42:106164
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0,12:42:106153
4,12:42:106152
1,12:42:106151
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1,12:42:106076
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4,12:42:106067
8,12:42:106066
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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