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2024-10-07 - 00:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26536 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 376 highest latencies:
System rack6slot4.osadl.org (updated Sun Oct 06, 2024 13:10:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32411:29:316431
331,11:24:076430
"maxima":[6429
011:24:076426
0,11:24:076425
0,11:24:076424
0,11:24:076423
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3,11:24:076341
0,11:24:076340
0,11:24:076339
4,11:24:076338
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2,11:24:076336
3,11:24:076335
7,11:24:076334
5,11:24:076333
7,11:24:076332
7,11:24:076331
6,11:24:076330
2,11:24:076329
4,11:24:076328
1,11:24:076327
3,11:24:076326
1,11:24:076325
3,11:24:076324
4,11:24:076323
8,11:24:076322
5,11:24:076321
5,11:24:076320
6,11:24:076319
13,11:24:076318
4,11:24:076317
14,11:24:076316
16,11:24:076315
10,11:24:076314
14,11:24:076313
12,11:24:076312
17,11:24:076311
16,11:24:076310
14,11:24:076309
18,11:24:076308
12,11:24:076307
21,11:24:076306
21,11:24:076305
27,11:24:076304
24,11:24:076303
28,11:24:076302
31,11:24:076301
26,11:24:076300
26,11:24:076299
31,11:24:076298
18,11:24:076297
32,11:24:076296
40,11:24:076295
24,11:24:076294
43,11:24:076293
25,11:24:076292
34,11:24:076291
41,11:24:076290
33,11:24:076289
40,11:24:076288
44,11:24:076287
49,11:24:076286
58,11:24:076285
51,11:24:076284
48,11:24:076283
57,11:24:076282
69,11:24:076281
83,11:24:076280
81,11:24:076279
74,11:24:076278
75,11:24:076277
98,11:24:076276
101,11:24:076275
105,11:24:076274
122,11:24:076273
137,11:24:076272
145,11:24:076271
143,11:24:076270
139,11:24:076269
177,11:24:076268
183,11:24:076267
200,11:24:076266
228,11:24:076265
243,11:24:076264
286,11:24:076263
299,11:24:076262
305,11:24:076261
325,11:24:076260
334,11:24:076259
327,11:24:076258
327,11:24:076257
355,11:24:076256
401,11:24:076255
407,11:24:076254
405,11:24:076253
438,11:24:076252
434,11:24:076251
409,11:24:076250
406,11:24:076249
367,11:24:076248
286,11:24:076247
266,11:24:076246
226,11:24:076245
204,11:24:076244
180,11:24:076243
188,11:24:076242
197,11:24:076241
220,11:24:076240
215,11:24:076239
237,11:24:076238
255,11:24:076237
257,11:24:076236
233,11:24:076235
162,11:24:076234
99,11:24:076233
105,11:24:076232
46,11:24:076231
43,11:24:076230
12,11:24:076229
8,11:24:076228
2,11:24:076227
6,11:24:076226
3,11:24:076225
5,11:24:076224
3,11:24:076223
3,11:24:076222
5,11:24:076221
2,11:24:076220
4,11:24:076219
3,11:24:076218
7,11:24:076217
15,11:24:076216
13,11:24:076215
15,11:24:076214
5,11:24:076213
12,11:24:076212
8,11:24:076211
6,11:24:076210
3,11:24:076209
3,11:24:076208
2,11:24:076207
2,11:24:076206
2,11:24:076205
1,11:24:076204
3,11:24:076203
1,11:24:076202
4,11:24:076201
2,11:24:076200
0,11:24:076199
3,11:24:076198
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2,11:24:076189
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3,11:24:076175
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0,11:24:076153
4,11:24:076152
1,11:24:076151
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4,11:24:076067
8,11:24:076066
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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