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2021-11-28 - 01:06

Intel(R) Celeron(R) CPU N3350 @ 1.10GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26432 SMIs that occured during the measurement.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot4.osadl.org (updated Sat Nov 27, 2021 12:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2615799361358,2cyclictest26140-21kworker/0:212:05:450
2615799343340,2cyclictest22529-21kworker/0:010:26:520
2615799341338,2cyclictest368-21kworker/0:111:09:590
2615799341338,2cyclictest18534-21kworker/0:209:51:180
2615799331328,2cyclictest18534-21kworker/0:209:57:120
2615799328326,1cyclictest368-21kworker/0:111:35:430
2615799327324,2cyclictest368-21kworker/0:111:11:340
2615799327324,2cyclictest368-21kworker/0:110:56:180
2615799327324,2cyclictest18534-21kworker/0:209:18:250
2615799327324,2cyclictest18534-21kworker/0:208:57:470
2615799327324,2cyclictest18534-21kworker/0:207:31:270
2615799326323,2cyclictest18534-21kworker/0:209:45:200
2615799326323,2cyclictest18534-21kworker/0:209:28:080
2615799326323,2cyclictest18534-21kworker/0:209:12:320
2615799326323,2cyclictest18534-21kworker/0:207:57:410
2615799324321,2cyclictest368-21kworker/0:111:47:050
2615799324321,2cyclictest22529-21kworker/0:010:34:440
2615799324321,2cyclictest22529-21kworker/0:010:20:010
2615799324321,2cyclictest18534-21kworker/0:207:29:200
2615799323320,2cyclictest26140-21kworker/0:212:17:000
2615799323320,2cyclictest26140-21kworker/0:212:10:530
2615799323320,2cyclictest18534-21kworker/0:208:27:580
2615799322319,2cyclictest368-21kworker/0:111:57:160
2615799322319,2cyclictest368-21kworker/0:111:34:070
2615799322319,2cyclictest3590-21kworker/0:012:33:100
2615799322319,2cyclictest22529-21kworker/0:010:36:100
2615799322319,2cyclictest22529-21kworker/0:010:14:060
2615799322319,2cyclictest18534-21kworker/0:208:50:300
2615799322319,2cyclictest18534-21kworker/0:207:37:470
2615799321319,1cyclictest18534-21kworker/0:208:36:500
2615799321318,2cyclictest26140-21kworker/0:212:01:540
2615799321318,2cyclictest22529-21kworker/0:010:08:010
2615799321318,2cyclictest18534-21kworker/0:208:18:570
2615799321318,2cyclictest18534-21kworker/0:207:13:250
2615799320317,2cyclictest368-21kworker/0:111:53:580
2615799320317,2cyclictest368-21kworker/0:111:19:390
2615799320317,2cyclictest26140-21kworker/0:212:21:020
2615799320317,2cyclictest18534-21kworker/0:210:01:490
2615799320317,2cyclictest18534-21kworker/0:208:22:350
2615799320317,2cyclictest18534-21kworker/0:208:08:020
2615899319299,8cyclictest18018-21kworker/1:210:00:131
2615799319316,2cyclictest368-21kworker/0:111:24:330
2615799319316,2cyclictest22529-21kworker/0:010:15:430
2615799319316,2cyclictest18534-21kworker/0:209:37:320
2615799319316,2cyclictest18534-21kworker/0:209:00:520
2615799319316,2cyclictest18534-21kworker/0:208:46:560
2615799318315,2cyclictest368-21kworker/0:111:42:080
2615799318315,2cyclictest368-21kworker/0:111:00:320
2615799318315,2cyclictest18534-21kworker/0:209:07:360
2615799317315,1cyclictest3590-21kworker/0:012:28:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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