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2024-07-21 - 00:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26438 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot4.osadl.org (updated Thu Jul 18, 2024 13:10:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32411:59:426431
331,11:54:186430
"maxima":[6429
011:54:186426
0,11:54:186425
0,11:54:186424
0,11:54:186423
0,11:54:186422
0,11:54:186421
0,11:54:186420
0,11:54:186419
0,11:54:186418
0,11:54:186417
0,11:54:186416
0,11:54:186415
0,11:54:186414
0,11:54:186413
0,11:54:186412
0,11:54:186411
0,11:54:186410
0,11:54:186409
0,11:54:186408
0,11:54:186407
0,11:54:186406
0,11:54:186405
0,11:54:186404
0,11:54:186403
0,11:54:186402
0,11:54:186401
0,11:54:186400
0,11:54:186399
0,11:54:186398
0,11:54:186397
0,11:54:186396
0,11:54:186395
0,11:54:186394
0,11:54:186393
0,11:54:186392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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