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2021-01-26 - 19:36

Intel(R) Celeron(R) CPU N3350 @ 1.10GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26378 SMIs that occured during the measurement.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot4.osadl.org (updated Tue Jan 26, 2021 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1401599319316,2cyclictest0-21swapper/110:10:041
14015993190,1cyclictest0-21swapper/109:40:021
1401599317315,1cyclictest0-21swapper/111:18:091
14014993150,313cyclictest0-21swapper/007:05:020
1401599314310,2cyclictest584-21avahi-daemon12:32:031
1401599313310,2cyclictest0-21swapper/111:23:251
1401599313310,2cyclictest0-21swapper/111:03:061
1401599313310,2cyclictest0-21swapper/110:03:441
1401599312310,1cyclictest0-21swapper/108:56:491
1401599312309,2cyclictest0-21swapper/107:26:461
1401499311308,2cyclictest30877-21kworker/0:111:27:500
1401599310308,1cyclictest0-21swapper/108:07:231
1401599310308,1cyclictest0-21swapper/107:57:361
1401599310307,2cyclictest25774-21kworker/1:111:12:251
1401599309306,2cyclictest19787-21kworker/1:007:24:371
1401499309307,1cyclictest1860-21kworker/0:212:12:570
1401599308304,2cyclictest19669-21runrttasks07:16:131
1401599307305,1cyclictest0-21swapper/111:31:531
1401599307305,1cyclictest0-21swapper/108:04:431
1401599307304,2cyclictest19787-21kworker/1:007:32:361
1401599307304,2cyclictest0-21swapper/111:35:501
1401599307304,2cyclictest0-21swapper/108:21:031
1401499307305,1cyclictest0-21swapper/007:04:560
1401599306304,1cyclictest13420-21kworker/1:211:07:081
1401599306303,2cyclictest304-21kworker/1:112:00:441
1401599306303,2cyclictest13420-21kworker/1:210:34:541
1401599306303,2cyclictest0-21swapper/110:36:371
1401599305302,2cyclictest0-21swapper/109:36:011
1401599305302,2cyclictest0-21swapper/109:27:231
1401599304301,2cyclictest0-21swapper/112:06:241
1401599304301,2cyclictest0-21swapper/108:14:111
14015993041,2cyclictest8774-21cstates10:15:391
1401499304301,2cyclictest6125-21kworker/0:210:31:060
1401499304301,2cyclictest19887-21kworker/0:007:23:390
14014993040,301cyclictest30875-21chrt11:24:520
1401599303301,1cyclictest25007-21kworker/1:010:11:411
1401599303301,1cyclictest0-21swapper/108:28:161
1401599303300,2cyclictest25007-21kworker/1:010:21:151
1401599303300,2cyclictest19787-21kworker/1:007:42:431
1401599303300,2cyclictest0-21swapper/111:49:201
1401599303300,2cyclictest0-21swapper/111:00:571
1401599303300,2cyclictest0-21swapper/109:17:261
1401499303300,2cyclictest1860-21kworker/0:211:38:100
1401499303298,3cyclictest1860-21kworker/0:211:53:490
1401599302299,2cyclictest0-21swapper/110:48:481
1401599302299,2cyclictest0-21swapper/109:29:401
1401599302299,2cyclictest0-21swapper/108:44:071
1401499302300,1cyclictest0-21swapper/012:31:470
1401499302300,1cyclictest0-21swapper/011:18:370
1401499302299,2cyclictest19658-21kworker/0:309:13:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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