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2024-07-27 - 03:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26524 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot4.osadl.org (updated Sat Jul 27, 2024 01:11:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32411:29:316431
331,11:24:076430
"maxima":[6429
011:24:076426
0,11:24:076425
0,11:24:076424
0,11:24:076423
0,11:24:076422
0,11:24:076421
0,11:24:076420
0,11:24:076419
0,11:24:076418
0,11:24:076417
0,11:24:076416
0,11:24:076415
0,11:24:076414
0,11:24:076413
0,11:24:076412
0,11:24:076411
0,11:24:076410
0,11:24:076409
0,11:24:076408
0,11:24:076407
0,11:24:076406
0,11:24:076405
0,11:24:076404
0,11:24:076403
0,11:24:076402
0,11:24:076401
0,11:24:076400
0,11:24:076399
0,11:24:076398
0,11:24:076397
0,11:24:076396
0,11:24:076395
0,11:24:076394
0,11:24:076393
0,11:24:076392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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