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2022-05-25 - 09:18

x86 Intel Celeron N3350 @1100 MHz, Linux 5.15.32-rt39 (Profile)

Latency plot of system in rack #6, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26434 SMIs that occured during the measurement.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot4.osadl.org (updated Fri May 20, 2022 00:43:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2932599339336,2cyclictest0-21swapper/016:53:300
2932599333331,1cyclictest0-21swapper/020:58:230
2932599332330,1cyclictest0-21swapper/021:12:420
2932599332329,2cyclictest18368-21kworker/0:223:07:550
2932599332329,2cyclictest18368-21kworker/0:223:07:540
29325993320,330cyclictest0-21swapper/017:54:560
2932599331329,1cyclictest0-21swapper/022:12:180
2932599324321,2cyclictest15682-21kworker/0:122:51:360
2932599324319,3cyclictest22822-21df_inode18:13:430
2932599323321,1cyclictest0-21swapper/019:54:480
2932599322320,1cyclictest0-21swapper/021:15:320
2932599322319,2cyclictest0-21swapper/020:32:460
2932599320317,2cyclictest2962-21ssh22:21:370
2932599320317,2cyclictest25078-21kworker/0:200:19:530
2932699319316,2cyclictest18433-21kworker/1:100:17:351
2932599319317,1cyclictest0-21swapper/020:22:470
2932599318315,2cyclictest30451-21kworker/0:116:27:500
2932599318315,2cyclictest0-21swapper/000:27:490
2932599317314,2cyclictest9935-21kworker/0:219:29:150
2932599315313,1cyclictest0-21swapper/017:41:490
2932599315312,2cyclictest0-21swapper/023:24:260
2932599315312,2cyclictest0-21swapper/020:48:170
2932599315311,2cyclictest15682-21kworker/0:122:24:130
29325993150,313cyclictest0-21swapper/023:17:200
2932599314312,1cyclictest0-21swapper/018:39:400
29325993140,312cyclictest0-21swapper/022:31:200
2932599313311,1cyclictest0-21swapper/000:35:060
2932599313310,2cyclictest0-21swapper/021:47:390
29325993130,311cyclictest0-21swapper/019:40:580
2932599312310,1cyclictest0-21swapper/023:55:570
2932599312309,2cyclictest25078-21kworker/0:200:10:160
2932599312308,2cyclictest6225-21kworker/0:021:40:460
2932599311308,2cyclictest3153-21kworker/0:119:20:250
2932599311308,2cyclictest2183-21kworker/0:121:33:130
2932599311308,2cyclictest15682-21kworker/0:121:55:010
2932599311308,2cyclictest0-21swapper/023:50:550
2932599311308,2cyclictest0-21swapper/021:26:320
2932599311307,3cyclictest2927-21kworker/0:223:31:250
2932599311307,3cyclictest18368-21kworker/0:223:02:460
2932599311305,5cyclictest6955-21kworker/0:220:41:060
29325993110,309cyclictest0-21swapper/018:43:590
2932699310307,2cyclictest2396-21kworker/1:219:36:481
2932599310308,1cyclictest0-21swapper/022:38:510
2932599310307,2cyclictest27101-21kworker/0:220:13:190
2932599310307,2cyclictest0-21swapper/020:20:130
2932599309307,1cyclictest0-21swapper/022:56:400
2932599309306,2cyclictest0-21swapper/017:27:420
29325993090,307cyclictest0-21swapper/022:04:370
2932599308305,2cyclictest22842-21kworker/0:119:59:270
2932599308305,2cyclictest0-21swapper/023:39:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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