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2025-03-22 - 16:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Sat Mar 22, 2025 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950600,0irq/26-eth1-rx-0-21swapper/307:05:463
110050600,0irq/25-eth00-21swapper/207:09:342
110050600,0irq/25-eth00-21swapper/107:06:071
117950400,0irq/26-eth1-rx-0-21swapper/007:07:240
351180,0ktimersoftd/311844-21sshd12:35:053
1815999180,0cyclictest26360-21sshd09:42:562
1815799180,0cyclictest1613-21sshd09:55:490
1815799180,0cyclictest15840-21sshd12:32:220
1815799180,0cyclictest11009-21sshd12:22:420
1815899173,0cyclictest0-21swapper/109:46:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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