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2025-07-13 - 22:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Sun Jul 13, 2025 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050660,0irq/25-eth00-21swapper/307:05:183
110050660,0irq/25-eth00-21swapper/307:05:173
110050630,0irq/25-eth00-21swapper/107:05:451
110050630,0irq/25-eth00-21swapper/107:05:451
9950570,0irq/24-0000:00:0-21swapper/007:05:430
9950570,0irq/24-0000:00:0-21swapper/007:05:430
110050560,0irq/25-eth00-21swapper/207:05:192
110050560,0irq/25-eth00-21swapper/207:05:182
1528799201,0cyclictest17056-21id10:36:560
1528799180,0cyclictest1453-21nfsd12:19:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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