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2024-02-24 - 17:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Sat Feb 24, 2024 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950650,0irq/26-eth1-rx-0-21swapper/307:05:173
110050580,0irq/25-eth00-21swapper/107:07:161
110050550,0irq/25-eth00-21swapper/207:06:002
117950470,0irq/26-eth1-rx-0-21swapper/007:06:500
271180,0ktimersoftd/227483-21chrt08:29:292
2184099180,0cyclictest27089-21sshd10:28:241
21841991615,0cyclictest0-21swapper/210:13:252
21839991611,0cyclictest0-21swapper/012:00:580
21839991514,0cyclictest0-21swapper/011:27:040
110050150,0irq/25-eth021779-21sshd09:19:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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