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2024-06-18 - 04:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Tue Jun 18, 2024 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050590,0irq/25-eth00-21swapper/319:09:313
110050590,0irq/25-eth00-21swapper/119:05:231
110050550,0irq/25-eth00-21swapper/219:06:232
3220124823,0sleep00-21swapper/019:08:020
3242799190,0cyclictest16494-21sshd00:00:361
3242899160,0cyclictest0-21swapper/200:07:112
32426991614,0cyclictest0-21swapper/000:21:250
32429991413,0cyclictest0-21swapper/323:44:593
32429991413,0cyclictest0-21swapper/323:15:353
32429991413,0cyclictest0-21swapper/322:00:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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