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2024-04-23 - 12:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Tue Apr 23, 2024 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950600,0irq/26-eth1-rx-0-21swapper/319:07:573
110050580,0irq/25-eth00-21swapper/119:07:571
110050460,0irq/25-eth00-21swapper/019:09:070
117950430,0irq/26-eth1-rx-0-21swapper/219:05:142
1255999182,0cyclictest0-21swapper/322:24:483
1255699180,0cyclictest8-21rcu_preempt22:20:000
1255799170,0cyclictest4481-21diskmemload21:15:171
12558991615,0cyclictest0-21swapper/222:43:192
1255899160,0cyclictest0-21swapper/222:21:432
1255699160,0cyclictest0-21swapper/022:51:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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