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2023-09-24 - 02:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Sat Sep 23, 2023 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050670,0irq/25-eth00-21swapper/107:05:181
117950600,0irq/26-eth1-rx-0-21swapper/307:07:023
110050560,0irq/25-eth00-21swapper/207:06:502
968924522,0sleep00-21swapper/007:06:200
117950280,0irq/26-eth1-rx-0-21swapper/107:10:001
10251991615,0cyclictest0-21swapper/211:24:392
1024999165,0cyclictest1861-21diskmemload10:57:560
1024999164,0cyclictest9049-21sshd11:08:260
1024999163,0cyclictest29268-21irqstats11:55:220
1025099150,0cyclictest0-21swapper/112:36:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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