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2024-07-27 - 08:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Sat Jul 27, 2024 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050650,0irq/25-eth00-21swapper/319:06:313
117950580,0irq/26-eth1-rx-0-21swapper/119:07:351
110050550,0irq/25-eth00-21swapper/219:05:332
117950440,0irq/26-eth1-rx-0-21swapper/019:09:080
335399180,0cyclictest22259-21sshd21:49:360
3353991711,0cyclictest0-21swapper/023:34:350
3354991615,0cyclictest0-21swapper/122:19:041
335499160,0cyclictest6447-21sshd21:14:291
351150,0ktimersoftd/330196-21sshd21:50:203
3355991512,0cyclictest0-21swapper/200:39:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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