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2024-10-15 - 03:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue Oct 15, 2024 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950690,0irq/26-eth1-rx-0-21swapper/019:09:260
110050640,0irq/25-eth00-21swapper/319:06:153
110050620,0irq/25-eth00-21swapper/119:05:121
110050590,0irq/25-eth00-21swapper/219:07:102
23012991716,0cyclictest0-21swapper/322:48:353
23011991615,0cyclictest0-21swapper/223:15:012
23010991513,0cyclictest0-21swapper/123:43:061
2301099150,0cyclictest20889-21bash00:10:201
110050150,0irq/25-eth00-21swapper/300:14:533
23012991413,0cyclictest0-21swapper/322:08:363
2301199140,0cyclictest0-21swapper/222:51:472
2301199140,0cyclictest0-21swapper/221:33:422
23010991413,0cyclictest0-21swapper/121:56:131
23010991411,0cyclictest0-21swapper/123:04:531
23010991411,0cyclictest0-21swapper/122:41:461
2301099140,0cyclictest0-21swapper/122:55:161
2301099140,0cyclictest0-21swapper/120:25:131
23009991413,0cyclictest110050irq/25-eth021:39:430
2300999140,0cyclictest0-21swapper/022:15:170
2300999140,0cyclictest0-21swapper/000:10:210
191140,0ktimersoftd/10-21swapper/123:57:161
110050140,0irq/25-eth00-21swapper/023:24:160
23012991312,0cyclictest0-21swapper/323:53:453
23012991311,0cyclictest1512-21sshd22:50:543
2301299130,0cyclictest0-21swapper/322:01:533
2301299130,0cyclictest0-21swapper/321:45:093
23011991311,0cyclictest0-21swapper/223:55:182
2301199130,0cyclictest31435-21perl22:55:152
2301199130,0cyclictest0-21swapper/223:35:202
23010991312,0cyclictest8598-21sshd21:47:511
23010991312,0cyclictest0-21swapper/100:29:131
23009991312,0cyclictest0-21swapper/000:00:530
2300999130,0cyclictest9283-21sshd22:37:340
2300999130,0cyclictest1977-21bash23:50:110
2300999130,0cyclictest0-21swapper/022:02:100
2300999130,0cyclictest0-21swapper/021:43:060
110050130,0irq/25-eth00-21swapper/122:37:351
110050130,0irq/25-eth00-21swapper/100:17:431
41120,0ktimersoftd/03570-21cp23:07:400
351120,0ktimersoftd/30-21swapper/321:57:413
351120,0ktimersoftd/30-21swapper/321:15:323
23012991211,0cyclictest0-21swapper/300:05:213
23012991210,0cyclictest16577-21sshd21:51:473
23012991210,0cyclictest0-21swapper/300:36:303
2301299120,0cyclictest0-21swapper/320:07:493
2301299120,0cyclictest0-21swapper/320:07:483
23011991211,0cyclictest9752-21bash23:54:022
23011991211,0cyclictest6354-21bash21:54:032
23011991211,0cyclictest24952-21sshd21:46:152
23011991211,0cyclictest11586-21sshd22:19:362
23011991211,0cyclictest0-21swapper/222:20:102
23011991210,0cyclictest6703-21bash00:32:082
2301199120,0cyclictest17882-21bash00:16:072
2301199120,0cyclictest0-21swapper/221:55:112
23010991211,0cyclictest24670-21sshd22:29:491
23010991211,0cyclictest0-21swapper/121:33:351
2301099120,0cyclictest6810-21sshd23:50:331
2301099120,0cyclictest0-21swapper/100:30:241
23009991211,0cyclictest0-21swapper/021:49:430
23009991210,0cyclictest0-21swapper/021:31:570
2300999120,0cyclictest0-21swapper/022:27:570
110050120,0irq/25-eth04655-21sshd23:38:141
110050120,0irq/25-eth020-21ksoftirqd/100:21:571
41110,0ktimersoftd/010140-21sshd00:09:240
271110,0ktimersoftd/20-21swapper/200:14:502
23012991111,0cyclictest0-21swapper/323:55:353
2301299111,0cyclictest0-21swapper/323:00:143
23012991110,0cyclictest0-21swapper/322:33:523
23012991110,0cyclictest0-21swapper/321:44:343
23012991110,0cyclictest0-21swapper/300:18:093
2301299110,0cyclictest6368-21sshd21:31:503
2301299110,0cyclictest0-21swapper/320:46:433
2301299110,0cyclictest0-21swapper/320:25:563
2301299110,0cyclictest0-21swapper/319:20:313
23011991111,0cyclictest0-21swapper/220:45:162
2301199110,0cyclictest0-21swapper/222:33:192
2301199110,0cyclictest0-21swapper/220:55:012
23009991111,0cyclictest0-21swapper/000:15:310
23009991110,0cyclictest0-21swapper/022:12:570
2300999110,0cyclictest23056-21sshd00:26:540
2300999110,0cyclictest0-21swapper/019:44:020
2300999110,0cyclictest0-21swapper/019:30:550
191110,0ktimersoftd/10-21swapper/122:30:021
110050110,0irq/25-eth08656-21sshd23:17:122
110050110,0irq/25-eth021231-21bash00:04:193
110050110,0irq/25-eth00-21swapper/322:42:493
110050110,0irq/25-eth00-21swapper/221:27:272
110050110,0irq/25-eth00-21swapper/200:21:052
41100,0ktimersoftd/09031-21sshd23:17:140
41100,0ktimersoftd/07195-21smart_sda23:35:200
41100,0ktimersoftd/014929-21diskmemload00:37:130
41100,0ktimersoftd/00-21swapper/023:32:050
351100,0ktimersoftd/30-21swapper/320:13:023
271100,0ktimersoftd/20-21swapper/221:21:362
2301299109,0cyclictest0-21swapper/323:27:343
2301299109,0cyclictest0-21swapper/322:39:163
2301299109,0cyclictest0-21swapper/320:23:153
2301299101,0cyclictest6523-21sshd00:21:433
23012991010,0cyclictest0-21swapper/320:39:183
23012991010,0cyclictest0-21swapper/319:58:513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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