You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-05-30 - 20:47

x86 Intel Xeon E3-1220L V2 @2300 MHz, Linux 4.4.39-rt50+ (Profile)

Latency plot of system in rack #7, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot0.osadl.org (updated Tue May 30, 2023 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950600,0irq/26-eth1-rx-0-21swapper/307:05:543
110050580,0irq/25-eth00-21swapper/107:05:541
9950390,0irq/24-0000:00:0-21swapper/007:05:050
2433523823,0sleep20-21swapper/207:08:112
2474999190,0cyclictest9130-21sshd10:26:061
24751991716,0cyclictest0-21swapper/310:43:003
110050160,0irq/25-eth020365-21sshd10:01:180
24751991512,0cyclictest110050irq/25-eth009:49:553
24749991512,0cyclictest32233-21sshd12:03:571
2474999151,0cyclictest0-21swapper/110:49:381
2474999150,0cyclictest0-21swapper/111:56:041
24748991514,0cyclictest0-21swapper/012:31:090
24748991514,0cyclictest0-21swapper/007:35:250
41140,0ktimersoftd/00-21swapper/010:32:050
24751991411,0cyclictest11433-21sshd09:24:573
24750991413,0cyclictest0-21swapper/210:36:562
24750991412,0cyclictest0-21swapper/209:50:492
2475099140,0cyclictest0-21swapper/210:48:332
24749991411,0cyclictest0-21swapper/111:31:411
24748991413,0cyclictest28785-21bash10:28:190
24748991411,0cyclictest30058-21sshd11:45:590
2474899140,0cyclictest29077-21sshd12:21:100
110050140,0irq/25-eth08333-21sshd09:48:111
24751991312,0cyclictest8983-21sshd11:15:253
24751991312,0cyclictest0-21swapper/311:54:203
24751991312,0cyclictest0-21swapper/310:59:303
24751991312,0cyclictest0-21swapper/310:10:573
2475199130,0cyclictest17533-21sshd10:34:113
2475199130,0cyclictest0-21swapper/309:40:313
24750991312,0cyclictest0-21swapper/211:47:062
24750991312,0cyclictest0-21swapper/210:03:312
24750991312,0cyclictest0-21swapper/209:33:522
24750991311,0cyclictest0-21swapper/212:38:562
24750991311,0cyclictest0-21swapper/209:15:582
2475099130,0cyclictest0-21swapper/211:29:202
2475099130,0cyclictest0-21swapper/211:11:052
24749991311,0cyclictest0-21swapper/111:03:061
2474999130,0cyclictest1512-21sshd09:53:591
2474999130,0cyclictest0-21swapper/110:33:431
2474999130,0cyclictest0-21swapper/109:34:341
24748991313,0cyclictest0-21swapper/009:33:540
24748991312,0cyclictest2302-21bash12:07:420
24748991312,0cyclictest0-21swapper/011:18:400
24748991311,0cyclictest16379-21diskmemload12:10:510
110050130,0irq/25-eth09601-21sshd12:11:593
110050130,0irq/25-eth029553-21sshd10:06:181
41120,0ktimersoftd/00-21swapper/009:37:560
351120,0ktimersoftd/328306-21sshd12:03:303
351120,0ktimersoftd/30-21swapper/312:38:003
24751991212,0cyclictest0-21swapper/310:50:053
24751991212,0cyclictest0-21swapper/309:55:233
24751991211,0cyclictest0-21swapper/312:27:123
24751991211,0cyclictest0-21swapper/311:33:253
24751991211,0cyclictest0-21swapper/311:03:343
24751991210,0cyclictest20869-21sshd11:27:233
24751991210,0cyclictest0-21swapper/312:18:083
24751991210,0cyclictest0-21swapper/310:46:573
24751991210,0cyclictest0-21swapper/309:31:483
2475199120,0cyclictest0-21swapper/311:42:573
2475199120,0cyclictest0-21swapper/310:17:413
2475199120,0cyclictest0-21swapper/310:17:413
2475099129,0cyclictest0-21swapper/210:26:152
24750991212,0cyclictest0-21swapper/209:42:552
24750991211,0cyclictest20579-21sshd11:06:062
24750991211,0cyclictest17020-21sshd12:26:582
24750991211,0cyclictest15624-21sshd11:19:482
24750991211,0cyclictest0-21swapper/212:18:492
24750991211,0cyclictest0-21swapper/212:14:452
24750991211,0cyclictest0-21swapper/212:04:262
24750991211,0cyclictest0-21swapper/211:31:382
24750991211,0cyclictest0-21swapper/210:57:302
24750991211,0cyclictest0-21swapper/210:17:052
24750991211,0cyclictest0-21swapper/210:17:052
24750991211,0cyclictest0-21swapper/210:05:282
24750991211,0cyclictest0-21swapper/209:05:312
24750991210,0cyclictest0-21swapper/212:07:332
24750991210,0cyclictest0-21swapper/211:40:082
24750991210,0cyclictest0-21swapper/208:19:242
24750991210,0cyclictest0-21swapper/208:08:432
2475099120,0cyclictest1512-21sshd09:35:572
2475099120,0cyclictest0-21swapper/210:32:042
2475099120,0cyclictest0-21swapper/209:29:052
2475099120,0cyclictest0-21swapper/207:20:282
24749991212,0cyclictest0-21swapper/110:55:541
24749991211,0cyclictest3091-21sshd12:39:381
24749991211,0cyclictest0-21swapper/111:14:571
24749991211,0cyclictest0-21swapper/110:02:141
24749991211,0cyclictest0-21swapper/109:38:111
24748991212,0cyclictest0-21swapper/010:16:320
24748991212,0cyclictest0-21swapper/010:16:320
24748991212,0cyclictest0-21swapper/008:20:290
24748991211,0cyclictest0-21swapper/012:39:590
24748991211,0cyclictest0-21swapper/011:51:400
24748991211,0cyclictest0-21swapper/011:42:290
24748991210,0cyclictest110050irq/25-eth010:59:370
2474899120,0cyclictest0-21swapper/009:59:060
2475199119,0cyclictest0-21swapper/309:07:383
24751991111,0cyclictest0-21swapper/311:08:343
24751991111,0cyclictest0-21swapper/310:06:043
24751991111,0cyclictest0-21swapper/308:06:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional