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2022-06-30 - 18:29

x86 Intel Xeon E3-1220L V2 @2300 MHz, Linux 4.4.39-rt50+ (Profile)

Latency plot of system in rack #7, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack7slot0.osadl.org (updated Thu Jun 30, 2022 12:45:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950650,0irq/26-eth1-rx-0-21swapper/307:05:203
110050630,0irq/25-eth00-21swapper/107:05:201
110050620,0irq/25-eth00-21swapper/207:06:282
110050530,0irq/25-eth00-21swapper/007:07:480
117950260,0irq/26-eth1-rx-0-21swapper/107:10:001
32574992117,0cyclictest110050irq/25-eth012:19:590
32576991615,0cyclictest0-21swapper/209:55:102
32577991514,0cyclictest0-21swapper/309:38:123
32575991514,0cyclictest0-21swapper/112:16:431
32577991413,0cyclictest32463-21sshd11:54:553
32577991413,0cyclictest0-21swapper/310:40:063
32577991413,0cyclictest0-21swapper/310:29:193
32576991413,0cyclictest0-21swapper/211:50:242
3257699140,0cyclictest0-21swapper/210:22:142
32575991413,0cyclictest0-21swapper/112:08:501
32574991413,0cyclictest24182-21diskmemload11:00:000
32574991413,0cyclictest0-21swapper/011:37:050
32574991413,0cyclictest0-21swapper/009:26:020
3257499140,0cyclictest0-21swapper/009:19:460
110050140,0irq/25-eth05113-21sshd12:23:583
110050140,0irq/25-eth00-21swapper/311:10:533
9950130,0irq/24-0000:00:0-21swapper/010:08:270
351130,0ktimersoftd/30-21swapper/309:54:133
32577991311,0cyclictest24182-21diskmemload10:52:463
32577991311,0cyclictest24182-21diskmemload10:52:463
32577991311,0cyclictest0-21swapper/310:30:073
32577991311,0cyclictest0-21swapper/309:30:113
3257799130,0cyclictest0-21swapper/311:00:543
3257799130,0cyclictest0-21swapper/310:17:063
3257799130,0cyclictest0-21swapper/309:49:073
32576991312,0cyclictest27366-21sshd12:05:022
32576991312,0cyclictest0-21swapper/211:40:592
32576991311,0cyclictest0-21swapper/210:40:222
3257699130,0cyclictest32020-21bash10:47:052
3257699130,0cyclictest0-21swapper/210:05:372
32575991311,0cyclictest0-21swapper/110:03:081
3257599130,0cyclictest0-21swapper/109:06:191
32574991312,0cyclictest10599-21sshd11:20:200
32574991312,0cyclictest10599-21sshd11:20:200
3257499130,0cyclictest0-21swapper/012:00:180
3257499130,0cyclictest0-21swapper/011:56:080
3257499130,0cyclictest0-21swapper/009:58:470
271130,0ktimersoftd/20-21swapper/212:10:242
110050130,0irq/25-eth026221-21bash11:47:013
110050130,0irq/25-eth00-21swapper/311:31:063
41120,0ktimersoftd/00-21swapper/011:50:320
32577991212,0cyclictest0-21swapper/312:13:163
32577991212,0cyclictest0-21swapper/310:09:133
32577991212,0cyclictest0-21swapper/309:42:443
32577991211,0cyclictest0-21swapper/311:23:053
32577991211,0cyclictest0-21swapper/311:23:053
3257799120,0cyclictest10512-21unixbench_singl09:15:263
3257799120,0cyclictest0-21swapper/311:41:333
3257799120,0cyclictest0-21swapper/310:01:193
32576991211,0cyclictest2288-21sshd11:26:362
32576991211,0cyclictest19080-21sshd09:30:392
32576991211,0cyclictest0-21swapper/211:39:372
32576991211,0cyclictest0-21swapper/211:31:142
32576991211,0cyclictest0-21swapper/209:27:102
32576991211,0cyclictest0-21swapper/209:14:512
32576991210,0cyclictest110050irq/25-eth010:27:462
3257699120,0cyclictest0-21swapper/212:37:352
3257699120,0cyclictest0-21swapper/210:57:542
3257699120,0cyclictest0-21swapper/209:47:442
32575991212,0cyclictest24182-21diskmemload12:04:591
32575991212,0cyclictest0-21swapper/111:18:111
32575991211,0cyclictest16112-21sshd11:28:091
32575991211,0cyclictest0-21swapper/112:35:391
32575991211,0cyclictest0-21swapper/110:16:291
32575991211,0cyclictest0-21swapper/109:20:501
32575991210,0cyclictest24182-21diskmemload12:14:581
32575991210,0cyclictest24182-21diskmemload11:45:071
32575991210,0cyclictest0-21swapper/112:24:361
3257599120,0cyclictest0-21swapper/110:49:291
32574991211,0cyclictest0-21swapper/010:18:540
3257499120,0cyclictest0-21swapper/012:14:280
3257499120,0cyclictest0-21swapper/010:58:080
3257499120,0cyclictest0-21swapper/009:13:290
3257499120,0cyclictest0-21swapper/007:10:210
110050120,0irq/25-eth04447-21sshd11:09:040
110050120,0irq/25-eth018012-21sshd12:07:310
110050120,0irq/25-eth015965-21sshd10:05:551
110050120,0irq/25-eth00-21swapper/211:58:182
110050120,0irq/25-eth00-21swapper/009:51:450
9950110,0irq/24-0000:00:0-21swapper/110:55:591
41110,0ktimersoftd/00-21swapper/010:45:160
41110,0ktimersoftd/00-21swapper/009:37:440
41110,0ktimersoftd/00-21swapper/008:25:010
351110,0ktimersoftd/30-21swapper/310:20:433
32577991111,0cyclictest0-21swapper/310:46:513
32577991111,0cyclictest0-21swapper/309:23:263
32577991111,0cyclictest0-21swapper/308:47:333
32577991110,0cyclictest0-21swapper/308:03:383
3257799110,0cyclictest0-21swapper/308:11:253
3257799110,0cyclictest0-21swapper/307:59:003
3257799110,0cyclictest0-21swapper/307:30:463
32576991111,0cyclictest0-21swapper/212:23:092
32576991110,0cyclictest23218-21switchtime11:00:212
32576991110,0cyclictest20730-21bash10:53:012
32576991110,0cyclictest20730-21bash10:53:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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