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2023-03-31 - 01:52

x86 Intel Xeon E3-1220L V2 @2300 MHz, Linux 4.4.39-rt50+ (Profile)

Latency plot of system in rack #7, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack7slot0.osadl.org (updated Thu Mar 30, 2023 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050580,0irq/25-eth00-21swapper/307:08:123
110050580,0irq/25-eth00-21swapper/107:05:211
2545524825,0sleep00-21swapper/007:07:090
2556124622,0sleep20-21swapper/207:08:322
25946991716,0cyclictest20-21ksoftirqd/112:37:221
2594899160,0cyclictest10826-21sshd10:55:273
25947991613,0cyclictest0-21swapper/209:55:252
25948991514,0cyclictest0-21swapper/311:00:283
2594699150,0cyclictest31342-21sshd10:54:131
2594899140,0cyclictest0-21swapper/311:20:193
25947991413,0cyclictest0-21swapper/212:21:532
25947991413,0cyclictest0-21swapper/210:02:312
25947991413,0cyclictest0-21swapper/209:41:492
2594799140,0cyclictest3066-21sshd11:29:452
2594799140,0cyclictest3066-21sshd11:29:452
25946991413,0cyclictest0-21swapper/109:30:131
25946991411,0cyclictest0-21swapper/109:39:041
110050140,0irq/25-eth00-21swapper/009:11:450
110050140,0irq/25-eth00-21swapper/009:11:440
25948991312,0cyclictest0-21swapper/309:25:213
25948991311,0cyclictest4853-21sshd09:43:223
25948991310,0cyclictest10873-21sshd10:48:323
2594899130,0cyclictest8889-21sshd11:51:153
2594899130,0cyclictest0-21swapper/310:37:083
25947991312,0cyclictest24117-21sshd09:34:102
25947991311,0cyclictest0-21swapper/212:18:322
2594799130,0cyclictest7989-21sshd10:05:452
2594799130,0cyclictest1453-21nfsd10:55:232
2594799130,0cyclictest0-21swapper/210:37:352
2594799130,0cyclictest0-21swapper/209:15:062
25946991312,0cyclictest0-21swapper/112:11:211
25946991312,0cyclictest0-21swapper/112:11:211
25946991312,0cyclictest0-21swapper/110:09:301
25946991311,0cyclictest18-21rcuc/111:49:381
25946991310,0cyclictest28825-21sshd12:21:271
2594699130,0cyclictest191ktimersoftd/110:30:171
25945991312,0cyclictest31739-21sshd10:22:430
25945991312,0cyclictest0-21swapper/010:06:060
2594599130,0cyclictest0-21swapper/012:07:580
2594599130,0cyclictest0-21swapper/007:50:210
25948991212,0cyclictest110050irq/25-eth011:59:303
25948991212,0cyclictest0-21swapper/310:04:223
25948991211,0cyclictest17598-21diskmemload09:12:063
25948991211,0cyclictest17598-21diskmemload09:12:063
25948991211,0cyclictest0-21swapper/311:47:173
25948991211,0cyclictest0-21swapper/311:05:573
25948991211,0cyclictest0-21swapper/310:15:393
25948991211,0cyclictest0-21swapper/310:07:383
25948991211,0cyclictest0-21swapper/309:37:253
25948991211,0cyclictest0-21swapper/309:16:323
25948991210,0cyclictest1452-21nfsd12:11:493
25948991210,0cyclictest1452-21nfsd12:11:483
25948991210,0cyclictest0-21swapper/312:16:073
25948991210,0cyclictest0-21swapper/311:32:263
2594899120,0cyclictest22988-21sshd10:42:503
25947991212,0cyclictest29082-21sshd12:07:302
25947991211,0cyclictest0-21swapper/210:14:562
25947991211,0cyclictest0-21swapper/207:52:582
25947991210,0cyclictest0-21swapper/212:36:532
25947991210,0cyclictest0-21swapper/211:56:072
2594799120,0cyclictest18943-21sshd09:45:052
2594799120,0cyclictest12622-21sshd11:06:022
2594799120,0cyclictest0-21swapper/212:28:382
2594799120,0cyclictest0-21swapper/211:50:382
2594799120,0cyclictest0-21swapper/211:40:402
2594799120,0cyclictest0-21swapper/210:31:532
2594799120,0cyclictest0-21swapper/210:20:172
25946991212,0cyclictest0-21swapper/110:38:031
25946991212,0cyclictest0-21swapper/108:55:291
25946991211,0cyclictest0-21swapper/111:51:081
25946991211,0cyclictest0-21swapper/110:45:511
25946991211,0cyclictest0-21swapper/110:26:061
25946991210,0cyclictest0-21swapper/109:46:091
25946991210,0cyclictest0-21swapper/109:11:461
25946991210,0cyclictest0-21swapper/109:11:451
2594699120,0cyclictest0-21swapper/112:19:011
2594699120,0cyclictest0-21swapper/110:56:181
2594699120,0cyclictest0-21swapper/110:02:591
25945991211,0cyclictest8131-21sshd12:36:460
25945991211,0cyclictest17598-21diskmemload10:18:190
25945991211,0cyclictest17598-21diskmemload10:02:500
25945991211,0cyclictest0-21swapper/009:36:490
2594599120,0cyclictest0-21swapper/009:43:200
2594599120,0cyclictest0-21swapper/009:32:250
110050120,0irq/25-eth00-21swapper/112:09:421
110050120,0irq/25-eth00-21swapper/009:47:370
41110,0ktimersoftd/00-21swapper/011:55:270
41110,0ktimersoftd/00-21swapper/007:58:120
271110,0ktimersoftd/220596-21sshd11:17:262
25948991111,0cyclictest0-21swapper/310:25:443
25948991110,0cyclictest17598-21diskmemload09:58:283
25948991110,0cyclictest0-21swapper/309:46:363
25948991110,0cyclictest0-21swapper/309:20:553
2594899110,0cyclictest0-21swapper/311:36:233
2594899110,0cyclictest0-21swapper/311:10:183
25947991111,0cyclictest0-21swapper/212:01:202
25947991111,0cyclictest0-21swapper/211:35:112
25947991111,0cyclictest0-21swapper/211:31:152
25947991111,0cyclictest0-21swapper/209:52:092
25947991111,0cyclictest0-21swapper/208:35:302
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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