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2025-07-12 - 13:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Sat Jul 12, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050610,0irq/25-eth00-21swapper/119:05:431
110050600,0irq/25-eth00-21swapper/319:05:013
110050600,0irq/25-eth00-21swapper/219:06:482
117950500,0irq/26-eth1-rx-0-21swapper/019:05:500
30520992120,0cyclictest14245-21id22:32:382
30520991918,0cyclictest8491-21sshd23:14:072
351180,0ktimersoftd/317551-21sshd22:20:053
271180,0ktimersoftd/216158-21sshd21:57:272
30521991512,0cyclictest0-21swapper/300:34:383
110050150,0irq/25-eth00-21swapper/322:53:553
41140,0ktimersoftd/022490-21sshd23:12:150
30521991413,0cyclictest5999-21consoletype22:15:353
30521991411,0cyclictest9032-21sshd22:03:093
30521991411,0cyclictest0-21swapper/300:03:163
3052199140,0cyclictest0-21swapper/321:10:323
3051999140,0cyclictest4227-21id22:21:541
3051999140,0cyclictest0-21swapper/123:22:531
30518991413,0cyclictest0-21swapper/000:25:330
3051899140,0cyclictest0-21swapper/023:02:430
110050140,0irq/25-eth00-21swapper/322:49:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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