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2026-03-10 - 14:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Tue Mar 10, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650630,0irq/26-eth1-rx-0-21swapper/307:08:443
112750590,0irq/25-eth00-21swapper/107:08:331
112750560,0irq/25-eth00-21swapper/207:07:152
112750490,0irq/25-eth00-21swapper/007:05:120
1349899190,0cyclictest22513-21sshd11:21:070
13501991817,0cyclictest36-21ksoftirqd/310:29:083
112750170,0irq/25-eth00-21swapper/111:54:051
13501991514,0cyclictest36-21ksoftirqd/312:34:573
1350099150,0cyclictest0-21swapper/209:00:132
13501991413,0cyclictest0-21swapper/311:10:023
13501991413,0cyclictest0-21swapper/310:00:193
13501991413,0cyclictest0-21swapper/309:45:343
13501991413,0cyclictest0-21swapper/309:23:173
13501991413,0cyclictest0-21swapper/309:23:163
1350199140,0cyclictest0-21swapper/310:51:263
1350199140,0cyclictest0-21swapper/309:00:173
1350099140,0cyclictest0-21swapper/209:40:142
1350099140,0cyclictest0-21swapper/209:40:132
1349999140,0cyclictest0-21swapper/109:49:121
13498991413,0cyclictest0-21swapper/011:44:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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