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2026-06-17 - 12:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Wed Jun 17, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120650590,0irq/26-eth1-rx-0-21swapper/119:07:161
112750580,0irq/25-eth00-21swapper/319:07:233
120650450,0irq/26-eth1-rx-0-21swapper/219:05:272
120650450,0irq/26-eth1-rx-0-21swapper/019:06:260
2537599211,0cyclictest17160-21sshd23:08:330
2537699190,0cyclictest28612-21date00:35:161
112750180,0irq/25-eth010174-21cp00:32:551
2537799160,0cyclictest0-21swapper/200:05:252
2537899150,0cyclictest0-21swapper/300:05:173
25377991513,0cyclictest0-21swapper/221:19:272
2537799150,0cyclictest0-21swapper/219:15:022
2537699150,0cyclictest0-21swapper/123:48:031
2537599150,0cyclictest0-21swapper/019:15:010
25378991412,0cyclictest1539-21sshd22:44:153
2537899141,0cyclictest19240-21rm00:25:253
2537899140,0cyclictest14267-21sshd23:12:223
2537899140,0cyclictest0-21swapper/300:10:133
25377991413,0cyclictest0-21swapper/223:42:482
2537799140,0cyclictest0-21swapper/222:29:442
25376991413,0cyclictest17293-21diskmemload22:29:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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