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2019-07-24 - 01:04

Intel(R) Xeon(R) CPU E3-1220L V2 @ 2.30GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #7, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Tue Jul 23, 2019 12:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114850830,0irq/25-eth00-21swapper/107:09:511
114850800,0irq/25-eth00-21swapper/307:09:403
114850620,0irq/25-eth00-21swapper/007:05:560
122750580,0irq/26-eth1-rx-0-21swapper/207:08:072
10150290,0irq/24-ahci[0000-21swapper/307:10:003
15255992612,0cyclictest4936-21sshd09:39:170
15258992517,0cyclictest11778-21perf12:10:003
1525899213,0cyclictest30482-21sshd09:22:183
15256992015,0cyclictest0-21swapper/107:54:171
1525599202,0cyclictest19795-21munin-run09:20:000
1525899190,0cyclictest23472-21sshd12:12:333
1525599190,0cyclictest3533-21perf11:20:000
15258991813,0cyclictest0-21swapper/309:15:063
15257991812,0cyclictest0-21swapper/208:45:072
1525799181,0cyclictest17998-21perf09:49:592
15256991815,0cyclictest0-21swapper/109:40:061
1525699180,0cyclictest26325-21turbostat10:29:591
1525599181,0cyclictest20693-21perf12:20:010
1525899170,0cyclictest4347-21ls12:40:013
1525799171,0cyclictest22267-21perf08:30:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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