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2024-12-09 - 22:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Mon Dec 09, 2024 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1100501120,0irq/25-eth00-21swapper/107:05:341
1100501070,0irq/25-eth00-21swapper/307:06:183
1100501010,0irq/25-eth00-21swapper/207:07:432
110050850,0irq/25-eth00-21swapper/007:06:390
13941992019,0cyclictest5894-21diskmemload11:17:243
1393899190,0cyclictest8021-21sshd10:50:300
41180,0ktimersoftd/023650-21sshd12:27:380
13939991712,0cyclictest15032-21rm09:15:111
13941991615,0cyclictest0-21swapper/310:26:123
1394099160,0cyclictest0-21swapper/208:30:182
1393899160,0cyclictest0-21swapper/012:35:200
110050160,0irq/25-eth019864-21sshd11:20:253
110050160,0irq/25-eth01542-21lldpd10:37:033
9950150,0irq/24-0000:00:20-21ksoftirqd/109:56:061
41150,0ktimersoftd/03958-21snmpd12:11:490
3399150,0migration/312830-21sshd09:10:413
13941991514,0cyclictest7477-21sshd12:12:283
13941991514,0cyclictest0-21swapper/309:19:443
13941991512,0cyclictest0-21swapper/312:32:073
13940991514,0cyclictest3958-21snmpd09:18:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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