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2021-07-26 - 19:32

Intel(R) Xeon(R) CPU E3-1220L V2 @ 2.30GHz, Linux 4.4.39-rt50+ (Profile)

Latency plot of system in rack #7, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Mon Jul 26, 2021 12:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950640,0irq/26-eth1-rx-0-21swapper/307:06:073
110050640,0irq/25-eth00-21swapper/107:06:331
110050550,0irq/25-eth00-21swapper/207:06:082
110050380,0irq/25-eth00-21swapper/007:08:120
3030699210,0cyclictest21926-21diskmemload11:21:041
3030899191,0cyclictest25913-21consoletype12:01:543
30306991817,0cyclictest27953-21sshd10:46:251
3030799160,0cyclictest30243-21cp11:17:522
3030699162,0cyclictest22401-21sshd11:56:571
30307991513,0cyclictest23333-21sshd10:28:072
30307991512,0cyclictest0-21swapper/209:59:412
110050150,0irq/25-eth00-21swapper/110:52:221
30308991413,0cyclictest0-21swapper/309:38:263
30307991412,0cyclictest0-21swapper/212:07:142
30307991411,0cyclictest13835-21sshd10:57:522
3030799140,0cyclictest25242-21sshd10:46:012
3030799140,0cyclictest0-21swapper/207:55:022
3030699143,0cyclictest0-21swapper/112:31:011
30306991413,0cyclictest0-21swapper/110:12:171
30306991411,0cyclictest0-21swapper/109:51:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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