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2024-04-26 - 08:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Fri Apr 26, 2024 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050630,0irq/25-eth00-21swapper/219:05:042
117950620,0irq/26-eth1-rx-0-21swapper/119:08:491
110050580,0irq/25-eth00-21swapper/319:07:523
354824530,0sleep00-21swapper/019:05:350
3979992014,0cyclictest7744-21sshd21:22:440
3979992014,0cyclictest0-21swapper/000:15:360
3979992013,0cyclictest31371-21sshd22:30:420
191190,0ktimersoftd/10-21swapper/100:23:021
41180,0ktimersoftd/0897-21sshd00:23:020
351180,0ktimersoftd/30-21swapper/300:23:033
398199160,0cyclictest0-21swapper/221:48:072
3982991514,0cyclictest0-21swapper/322:02:043
3982991514,0cyclictest0-21swapper/322:02:033
3980991511,0cyclictest29487-21sshd22:57:151
397999151,0cyclictest0-21swapper/021:13:400
110050150,0irq/25-eth00-21swapper/323:10:153
3982991413,0cyclictest0-21swapper/321:56:573
3981991413,0cyclictest0-21swapper/223:46:402
398199140,0cyclictest0-21swapper/222:48:032
3980991412,0cyclictest0-21swapper/122:00:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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