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2023-12-04 - 05:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Mon Dec 04, 2023 00:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050660,0irq/25-eth00-21swapper/319:09:303
117950640,0irq/26-eth1-rx-0-21swapper/119:09:291
110050590,0irq/25-eth00-21swapper/219:06:292
9950510,0irq/24-0000:00:0-21swapper/019:05:560
351180,0ktimersoftd/327725-21sshd22:44:133
636699150,0cyclictest0-21swapper/323:46:113
636599150,0cyclictest0-21swapper/221:40:202
6366991413,0cyclictest0-21swapper/322:07:193
6366991411,0cyclictest20285-21sshd22:23:423
6366991411,0cyclictest0-21swapper/300:03:303
6365991413,0cyclictest30417-21diskmemload22:26:332
6365991411,0cyclictest0-21swapper/223:43:482
636599141,0cyclictest0-21swapper/200:35:092
636599141,0cyclictest0-21swapper/200:35:082
6364991413,0cyclictest8526-21sshd22:26:081
6364991412,0cyclictest7512-21sshd21:34:401
636499140,0cyclictest0-21swapper/123:58:501
636399140,0cyclictest29823-21sshd21:17:380
636399140,0cyclictest0-21swapper/021:49:130
110050140,0irq/25-eth017500-21rm00:01:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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