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2025-04-26 - 10:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Sat Apr 26, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050590,0irq/25-eth00-21swapper/119:06:351
110050580,0irq/25-eth00-21swapper/319:05:473
110050550,0irq/25-eth00-21swapper/019:05:170
1139824722,0sleep20-21swapper/219:09:092
11535992019,0cyclictest0-21swapper/021:31:050
271190,0ktimersoftd/22076-21bash22:18:022
191190,0ktimersoftd/12075-21bash22:18:021
11536991815,0cyclictest0-21swapper/121:46:401
11538991514,0cyclictest0-21swapper/322:22:123
11538991514,0cyclictest0-21swapper/321:32:583
11538991514,0cyclictest0-21swapper/321:23:333
11537991514,0cyclictest28587-21sshd21:52:512
11537991514,0cyclictest10151-21sshd23:45:322
11536991512,0cyclictest0-21swapper/123:20:241
1448321412,0sleep114644-21sshd00:32:461
11538991413,0cyclictest0-21swapper/323:35:243
11538991413,0cyclictest0-21swapper/300:08:103
1153899140,0cyclictest0-21swapper/322:59:103
11537991413,0cyclictest23807-21sshd22:13:592
11537991413,0cyclictest0-21swapper/221:27:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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