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2024-04-20 - 19:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Sat Apr 20, 2024 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950590,0irq/26-eth1-rx-0-21swapper/307:05:433
117950560,0irq/26-eth1-rx-0-21swapper/107:06:101
110050560,0irq/25-eth00-21swapper/207:07:382
117950460,0irq/26-eth1-rx-0-21swapper/007:09:340
110050170,0irq/25-eth00-21swapper/211:28:262
11582991514,0cyclictest0-21swapper/012:12:010
1158299150,0cyclictest0-21swapper/012:28:450
110050150,0irq/25-eth00-21swapper/312:13:163
11584991413,0cyclictest0-21swapper/211:18:272
11583991413,0cyclictest0-21swapper/110:39:311
1158399140,0cyclictest18763-21sshd11:36:391
11582991413,0cyclictest110050irq/25-eth010:30:090
11582991411,0cyclictest25347-21bash11:02:290
11585991312,0cyclictest29544-21sshd10:14:123
11585991312,0cyclictest0-21swapper/311:43:253
11585991312,0cyclictest0-21swapper/310:02:083
11585991312,0cyclictest0-21swapper/309:18:123
1158599130,0cyclictest0-21swapper/312:03:103
1158599130,0cyclictest0-21swapper/311:37:583
1158599130,0cyclictest0-21swapper/310:40:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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