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2024-04-14 - 23:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot0.osadl.org (updated Sun Apr 14, 2024 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950600,0irq/26-eth1-rx-0-21swapper/307:05:313
110050600,0irq/25-eth00-21swapper/107:06:131
117950460,0irq/26-eth1-rx-0-21swapper/007:08:470
507424220,0sleep20-21swapper/207:07:262
535699211,0cyclictest21479-21sshd12:10:140
535699211,0cyclictest21479-21sshd12:10:130
535799190,0cyclictest2146-21id11:57:281
535999160,0cyclictest110050irq/25-eth010:37:173
5358991615,0cyclictest0-21swapper/210:34:272
535899160,0cyclictest0-21swapper/207:25:152
535999150,0cyclictest0-21swapper/312:38:343
5357991514,0cyclictest6757-21sshd10:35:131
5356991514,0cyclictest0-21swapper/011:33:320
535699150,0cyclictest0-21swapper/012:20:420
5359991413,0cyclictest29001-21sshd12:21:573
5359991413,0cyclictest23540-21sshd10:16:513
535999140,0cyclictest0-21swapper/312:04:473
535999140,0cyclictest0-21swapper/307:25:183
5357991411,0cyclictest0-21swapper/109:18:391
5356991413,0cyclictest0-21swapper/011:14:370
535699140,0cyclictest0-21swapper/010:51:150
271140,0ktimersoftd/20-21swapper/212:10:252
271140,0ktimersoftd/20-21swapper/212:10:242
5359991312,0cyclictest12007-21sshd09:38:453
5359991312,0cyclictest0-21swapper/309:27:013
535999130,0cyclictest0-21swapper/309:43:103
5358991312,0cyclictest5336-21sshd12:37:142
5358991312,0cyclictest0-21swapper/210:42:412
5358991312,0cyclictest0-21swapper/209:37:382
5358991310,0cyclictest29740-21diskmemload11:37:392
535899130,0cyclictest0-21swapper/212:25:572
5357991312,0cyclictest0-21swapper/109:24:571
5357991311,0cyclictest29740-21diskmemload12:21:241
5357991311,0cyclictest23850-21sshd11:31:241
535799130,0cyclictest0-21swapper/111:47:351
535799130,0cyclictest0-21swapper/110:34:381
535799130,0cyclictest0-21swapper/109:45:301
5356991312,0cyclictest0-21swapper/012:07:550
5356991312,0cyclictest0-21swapper/009:47:020
535699130,0cyclictest0-21swapper/011:27:020
110050130,0irq/25-eth00-21swapper/009:31:410
110050130,0irq/25-eth00-21swapper/009:26:200
5359991212,0cyclictest110050irq/25-eth011:47:353
5359991212,0cyclictest0-21swapper/309:13:183
5359991211,0cyclictest15422-21sshd11:07:233
5359991211,0cyclictest0-21swapper/310:45:333
5359991211,0cyclictest0-21swapper/309:55:153
5359991210,0cyclictest0-21swapper/312:33:143
5359991210,0cyclictest0-21swapper/311:20:593
5359991210,0cyclictest0-21swapper/309:51:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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