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2023-05-28 - 02:10

x86 Intel Xeon E3-1220L V2 @2300 MHz, Linux 4.4.39-rt50+ (Profile)

Latency plot of system in rack #7, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot0.osadl.org (updated Sat May 27, 2023 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050650,0irq/25-eth00-21swapper/107:07:051
117950560,0irq/26-eth1-rx-0-21swapper/307:09:453
814524420,0sleep20-21swapper/207:08:192
117950420,0irq/26-eth1-rx-0-21swapper/007:06:190
271180,0ktimersoftd/25379-21sshd12:08:372
8552991513,0cyclictest0-21swapper/311:53:343
8552991512,0cyclictest0-21swapper/309:55:253
8551991512,0cyclictest0-21swapper/210:20:112
8551991512,0cyclictest0-21swapper/210:20:102
8551991511,0cyclictest23953-21sshd09:51:072
8550991512,0cyclictest0-21swapper/112:36:011
854999150,0cyclictest20305-21sshd10:26:380
8552991413,0cyclictest19660-21sshd10:45:303
8552991413,0cyclictest0-21swapper/311:13:573
8552991413,0cyclictest0-21swapper/309:54:303
8551991413,0cyclictest32567-21diskmemload11:34:172
8549991413,0cyclictest20410-21munin-node10:15:290
8552991312,0cyclictest0-21swapper/312:32:293
8552991311,0cyclictest0-21swapper/310:35:373
855299130,0cyclictest0-21swapper/312:07:373
855299130,0cyclictest0-21swapper/310:12:433
855299130,0cyclictest0-21swapper/309:21:443
8551991312,0cyclictest15935-21sshd11:48:412
8551991312,0cyclictest0-21swapper/212:38:182
8551991312,0cyclictest0-21swapper/211:20:272
8551991311,0cyclictest23811-21sshd10:15:312
8551991311,0cyclictest0-21swapper/210:55:422
855199130,0cyclictest0-21swapper/211:56:222
855199130,0cyclictest0-21swapper/210:50:092
855199130,0cyclictest0-21swapper/210:48:162
855199130,0cyclictest0-21swapper/209:23:152
8550991312,0cyclictest23045-21sshd11:10:441
8550991312,0cyclictest0-21swapper/111:38:451
855099130,0cyclictest32567-21diskmemload11:53:081
8549991312,0cyclictest0-21swapper/010:21:580
8549991312,0cyclictest0-21swapper/010:21:580
8549991311,0cyclictest17363-21sshd09:12:100
8549991311,0cyclictest0-21swapper/011:21:410
8549991311,0cyclictest0-21swapper/009:40:030
854999130,0cyclictest32567-21diskmemload10:13:370
41130,0ktimersoftd/05392-21sshd11:19:280
271130,0ktimersoftd/22676-21sshd11:19:112
110050130,0irq/25-eth00-21swapper/311:36:233
110050130,0irq/25-eth00-21swapper/012:17:480
8552991212,0cyclictest0-21swapper/309:00:213
8552991211,0cyclictest32567-21diskmemload09:39:303
8552991211,0cyclictest21031-21sshd11:28:083
8552991211,0cyclictest20152-21sshd11:31:293
8552991211,0cyclictest0-21swapper/309:32:463
8552991211,0cyclictest0-21swapper/309:15:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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