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2024-04-25 - 23:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Thu Apr 25, 2024 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32118212559,60sleep30-21swapper/307:08:243
31818211958,20sleep20-21swapper/207:05:382
32044210752,50sleep00-21swapper/007:07:410
3186128456,23sleep10-21swapper/107:06:051
131052750,1sleep27382-21stress10:12:292
131052750,1sleep27382-21stress10:12:292
3243399646,42cyclictest0-21swapper/211:20:262
3243399646,42cyclictest0-21swapper/211:20:252
3243399636,41cyclictest0-21swapper/212:25:252
3243399626,45cyclictest0-21swapper/210:22:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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