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2025-04-18 - 18:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Fri Apr 18, 2025 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24179211755,23sleep10-21swapper/107:07:041
24371211353,55sleep20-21swapper/207:09:302
24056211249,57sleep00-21swapper/007:05:350
309742960,2sleep214012-21stress11:20:242
309742960,2sleep214012-21stress11:20:242
2406229367,21sleep30-21swapper/307:05:383
268702490,1sleep314011-21stress11:10:233
173652460,1sleep314013-21stress10:42:233
24511994317,23cyclictest0-21swapper/110:13:261
24511994317,23cyclictest0-21swapper/110:13:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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