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2024-06-15 - 22:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Sat Jun 15, 2024 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
529321260,1sleep212837-21stress10:09:022
26366211854,24sleep10-21swapper/107:06:541
26470211451,58sleep30-21swapper/307:08:173
26415211051,54sleep00-21swapper/007:07:340
2627029062,23sleep20-21swapper/207:05:392
26705994511,24cyclictest0-21swapper/009:35:560
26705994310,21cyclictest0-21swapper/012:17:320
26705994310,21cyclictest0-21swapper/012:17:320
26706994111,27cyclictest0-21swapper/112:20:331
26705994116,18cyclictest0-21swapper/007:17:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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