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2025-07-14 - 21:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Mon Jul 14, 2025 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4863212956,38sleep30-21swapper/307:09:493
4863212956,38sleep30-21swapper/307:09:493
1573821250,1sleep224257-21stress12:39:232
1573821250,1sleep224257-21stress12:39:232
2477121190,1sleep224257-21stress11:42:532
4737211350,58sleep00-21swapper/007:08:130
4737211350,58sleep00-21swapper/007:08:130
4594211351,57sleep10-21swapper/107:06:221
4594211351,57sleep10-21swapper/107:06:211
4611210547,53sleep20-21swapper/207:06:342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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