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2026-06-16 - 20:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Tue Jun 16, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5093212158,23sleep30-21swapper/307:07:463
2787521180,1sleep226104-21stress09:10:402
5212211654,20sleep20-21swapper/207:09:132
5037211555,20sleep00-21swapper/007:07:020
5256211454,21sleep10-21swapper/107:09:441
74292500,1sleep126106-21stress09:40:151
537999455,29cyclictest0-21swapper/009:55:320
537999455,29cyclictest0-21swapper/009:55:320
5380994211,28cyclictest0-21swapper/111:33:221
537999417,23cyclictest0-21swapper/010:55:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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