You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-09 - 11:57
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Wed Jul 09, 2025 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23060212764,57sleep30-21swapper/319:07:243
23218211854,23sleep20-21swapper/219:09:272
23006211351,57sleep10-21swapper/119:06:421
54442950,1sleep25447-21aten2_r7power_v22:15:152
54442950,1sleep25447-21aten2_r7power_v22:15:142
2325228353,24sleep00-21swapper/019:09:530
119912620,1sleep310083-21stress21:12:483
325002460,1sleep310085-21stress00:35:203
325002460,1sleep310085-21stress00:35:203
23361994215,24cyclictest0-21swapper/222:35:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional