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2022-09-25 - 14:24
/usr/bin/Xorg /usr/bin/Xorg

x86 Intel (undisclosed) @1600 MHz, Linux 4.9.20-rt16 (Profile)

Latency plot of system in rack #7, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot1.osadl.org (updated Sun Sep 25, 2022 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30065211754,58sleep20-21swapper/219:08:392
30034210750,52sleep10-21swapper/119:08:191
2801429670,21sleep30-21swapper/319:05:153
2975128552,26sleep00-21swapper/019:05:310
30313996711,45cyclictest0-21swapper/200:30:432
30313996512,41cyclictest0-21swapper/223:33:172
30313996512,41cyclictest0-21swapper/223:33:162
3031399626,40cyclictest0-21swapper/200:15:262
30313996012,38cyclictest0-21swapper/222:10:242
30313995814,40cyclictest0-21swapper/221:20:382
327042560,18sleep025741-21stress22:29:070
30313995615,38cyclictest0-21swapper/223:03:542
30313995615,38cyclictest0-21swapper/223:03:542
3031399558,44cyclictest0-21swapper/221:55:492
3031399557,45cyclictest0-21swapper/223:46:192
30313995515,37cyclictest0-21swapper/222:30:362
30313995512,40cyclictest0-21swapper/222:50:282
30313995512,40cyclictest0-21swapper/222:50:272
3031399549,42cyclictest0-21swapper/200:25:272
3031399548,26cyclictest0-21swapper/222:36:032
3031399548,26cyclictest0-21swapper/222:09:232
3031399548,26cyclictest0-21swapper/222:09:232
3031399547,26cyclictest0-21swapper/222:55:112
30313995414,37cyclictest0-21swapper/222:26:092
30313995414,20cyclictest0-21swapper/223:06:282
3031399537,43cyclictest0-21swapper/223:50:362
3031399537,25cyclictest0-21swapper/221:53:582
3031399537,16cyclictest0-21swapper/222:15:552
30313995314,15cyclictest0-21swapper/223:58:252
30313995314,15cyclictest0-21swapper/223:58:252
30313995313,21cyclictest0-21swapper/223:28:502
30313995313,21cyclictest0-21swapper/223:28:492
30313995313,20cyclictest0-21swapper/222:00:062
30313995312,38cyclictest0-21swapper/221:31:552
30313995213,36cyclictest0-21swapper/221:10:192
30313995213,17cyclictest0-21swapper/200:00:342
3031399519,18cyclictest0-21swapper/200:35:252
3031399519,18cyclictest0-21swapper/200:35:252
3031399517,24cyclictest0-21swapper/200:14:382
30313995114,19cyclictest0-21swapper/221:19:572
30313995111,16cyclictest0-21swapper/223:15:212
30313995110,18cyclictest0-21swapper/200:20:182
225382510,1sleep025738-21stress00:20:010
3031399507,40cyclictest0-21swapper/221:40:072
3031399507,23cyclictest0-21swapper/222:21:312
3031399505,19cyclictest0-21swapper/223:44:202
30313995014,33cyclictest0-21swapper/221:45:212
30313995013,34cyclictest0-21swapper/223:37:312
30313995013,16cyclictest0-21swapper/223:20:452
30313995013,16cyclictest0-21swapper/223:20:452
30313995010,17cyclictest0-21swapper/223:10:352
3031399499,19cyclictest0-21swapper/222:45:292
3031399499,19cyclictest0-21swapper/222:45:292
3031399496,17cyclictest0-21swapper/221:35:202
3031399496,17cyclictest0-21swapper/221:35:192
30313994910,17cyclictest0-21swapper/222:40:132
3031399486,39cyclictest0-21swapper/200:06:272
30313994810,20cyclictest0-21swapper/219:55:172
3031399479,16cyclictest0-21swapper/219:15:112
3031399477,20cyclictest0-21swapper/221:25:072
3031399476,20cyclictest0-21swapper/220:40:232
3031399468,20cyclictest0-21swapper/219:45:152
30313994613,16cyclictest0-21swapper/220:15:122
30313994610,18cyclictest0-21swapper/220:25:202
3031399459,18cyclictest0-21swapper/221:05:212
3031399459,18cyclictest0-21swapper/221:05:202
3031399457,20cyclictest0-21swapper/219:50:192
30313994513,15cyclictest0-21swapper/220:35:162
30313994512,14cyclictest0-21swapper/220:55:152
30313994511,16cyclictest0-21swapper/219:35:162
3031399449,17cyclictest0-21swapper/219:30:152
30313994412,14cyclictest0-21swapper/221:00:172
30313994411,16cyclictest0-21swapper/220:00:222
30313994411,15cyclictest0-21swapper/219:40:132
30313994410,16cyclictest0-21swapper/219:25:272
3031399435,22cyclictest0-21swapper/220:20:152
30313994312,14cyclictest0-21swapper/220:30:182
3031399426,13cyclictest0-21swapper/220:45:152
3031399425,20cyclictest0-21swapper/219:20:582
3031399425,20cyclictest0-21swapper/219:20:582
3031399425,19cyclictest0-21swapper/219:10:072
30313994110,14cyclictest0-21swapper/220:10:122
30311994114,24cyclictest0-21swapper/022:18:380
74012405,14sleep30-21swapper/320:30:253
3031399406,12cyclictest0-21swapper/220:50:212
30311994020,13cyclictest0-21swapper/000:25:120
30311994015,22cyclictest0-21swapper/021:44:470
30311994012,20cyclictest0-21swapper/021:15:300
3031399395,14cyclictest0-21swapper/220:06:272
30312993916,20cyclictest0-21swapper/121:39:011
30312993916,20cyclictest0-21swapper/121:39:011
30316993816,19cyclictest0-21swapper/322:42:203
3031199389,15cyclictest0-21swapper/000:10:260
3031199386,29cyclictest0-21swapper/021:25:430
30311993814,16cyclictest0-21swapper/000:05:060
30312993715,20cyclictest0-21swapper/123:35:161
30311993716,18cyclictest0-21swapper/022:39:380
30311993716,18cyclictest0-21swapper/000:36:400
30311993716,18cyclictest0-21swapper/000:36:390
30311993713,21cyclictest0-21swapper/023:38:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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