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2022-05-26 - 23:56

x86 Intel (undisclosed) @1600 MHz, Linux 4.9.20-rt16 (Profile)

Latency plot of system in rack #7, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot1.osadl.org (updated Fri May 20, 2022 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13597211756,56sleep20-21swapper/219:08:382
13610211452,57sleep00-21swapper/019:08:490
1371029264,23sleep30-21swapper/319:09:593
1163628554,26sleep10-21swapper/119:05:071
13822994811,26cyclictest0-21swapper/000:37:460
1382399442,33cyclictest0-21swapper/100:20:301
13823994410,21cyclictest0-21swapper/100:02:561
13823994310,22cyclictest0-21swapper/121:15:331
13822994018,15cyclictest0-21swapper/019:15:120
13822994011,26cyclictest0-21swapper/000:20:060
39502395,13sleep30-21swapper/319:55:113
215492395,13sleep00-21swapper/019:22:310
13825993920,16cyclictest0-21swapper/323:39:073
13824993912,24cyclictest0-21swapper/200:20:242
13822993915,17cyclictest0-21swapper/021:46:350
13822993914,22cyclictest0-21swapper/023:30:140
13822993910,18cyclictest0-21swapper/021:20:140
320262385,12sleep00-21swapper/020:52:220
178392385,13sleep30-21swapper/320:23:413
160572385,13sleep20-21swapper/219:14:202
13824993811,24cyclictest0-21swapper/223:30:322
13822993813,17cyclictest0-21swapper/000:15:290
158612375,12sleep00-21swapper/019:12:100
1382499376,16cyclictest0-21swapper/222:54:212
13824993716,18cyclictest0-21swapper/222:02:462
13824993711,23cyclictest0-21swapper/223:27:142
1382399379,19cyclictest0-21swapper/123:35:291
1382399378,20cyclictest0-21swapper/119:40:201
13823993723,12cyclictest0-21swapper/100:19:001
13823993720,15cyclictest0-21swapper/123:49:111
1382299378,16cyclictest0-21swapper/022:55:140
13822993714,16cyclictest0-21swapper/022:10:070
13822993714,16cyclictest0-21swapper/022:08:300
13822993714,16cyclictest0-21swapper/022:08:300
263012365,13sleep20-21swapper/219:32:282
248962365,10sleep30-21swapper/320:37:343
203402365,10sleep30-21swapper/320:29:433
154872365,10sleep30-21swapper/320:19:083
154222365,13sleep20-21swapper/220:18:202
13825993613,20cyclictest0-21swapper/322:29:433
13824993616,17cyclictest0-21swapper/222:11:102
1382399369,18cyclictest0-21swapper/123:05:321
1382399368,18cyclictest0-21swapper/121:10:141
1382399366,21cyclictest0-21swapper/121:45:291
13823993619,15cyclictest0-21swapper/122:53:241
13823993616,17cyclictest0-21swapper/123:05:031
13823993615,18cyclictest0-21swapper/100:30:231
13823993615,18cyclictest0-21swapper/100:30:221
1382299368,25cyclictest0-21swapper/000:25:320
1382299368,25cyclictest0-21swapper/000:25:310
1382299367,23cyclictest0-21swapper/019:35:220
13822993615,18cyclictest0-21swapper/023:20:020
13822993615,13cyclictest0-21swapper/023:35:350
13822993611,18cyclictest0-21swapper/019:40:230
129192365,13sleep00-21swapper/020:11:350
84212355,12sleep00-21swapper/020:04:460
32592355,13sleep30-21swapper/319:51:053
250152355,10sleep00-21swapper/020:38:540
240092355,13sleep20-21swapper/219:28:232
224242355,13sleep20-21swapper/220:31:182
202882355,12sleep20-21swapper/220:29:142
13824993521,12cyclictest0-21swapper/223:55:162
13824993516,16cyclictest0-21swapper/221:50:342
13824993513,19cyclictest0-21swapper/222:36:162
13824993513,19cyclictest0-21swapper/222:36:162
13824993511,21cyclictest0-21swapper/223:10:422
13824993511,21cyclictest0-21swapper/223:10:412
13824993511,21cyclictest0-21swapper/222:20:002
1382399358,20cyclictest0-21swapper/120:15:151
13823993521,12cyclictest0-21swapper/122:20:351
13823993519,14cyclictest0-21swapper/123:30:201
13823993519,14cyclictest0-21swapper/121:40:361
13823993517,16cyclictest0-21swapper/121:35:301
13823993516,16cyclictest0-21swapper/122:15:201
13823993516,16cyclictest0-21swapper/121:55:361
13823993514,18cyclictest0-21swapper/121:30:231
13823993514,18cyclictest0-21swapper/121:30:221
13823993513,19cyclictest0-21swapper/122:05:481
13823993513,19cyclictest0-21swapper/122:05:481
13823993510,18cyclictest0-21swapper/120:50:191
1382299356,23cyclictest0-21swapper/023:55:070
1382299356,23cyclictest0-21swapper/020:30:050
1382299354,25cyclictest0-21swapper/020:15:240
131902355,10sleep30-21swapper/320:14:393
248272345,13sleep20-21swapper/220:36:442
158752345,10sleep00-21swapper/020:20:110
13825993415,16cyclictest0-21swapper/322:45:443
13825993411,20cyclictest0-21swapper/321:39:453
13825993411,20cyclictest0-21swapper/321:16:453
13825993411,15cyclictest0-21swapper/320:55:163
13825993410,21cyclictest0-21swapper/323:09:253
13825993410,21cyclictest0-21swapper/321:20:243
13824993416,15cyclictest0-21swapper/223:20:322
13824993416,15cyclictest0-21swapper/223:15:042
13824993415,16cyclictest0-21swapper/222:30:142
1382399345,20cyclictest0-21swapper/122:30:161
13823993420,12cyclictest0-21swapper/122:35:371
13823993420,12cyclictest0-21swapper/122:35:361
13823993418,14cyclictest0-21swapper/123:55:291
13823993418,14cyclictest0-21swapper/123:40:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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