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2023-02-06 - 21:19

x86 Intel (undisclosed) @1600 MHz, Linux 4.9.20-rt16 (Profile)

Latency plot of system in rack #7, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack7slot1.osadl.org (updated Mon Feb 06, 2023 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3225921190,1sleep29414-21stress11:13:122
1071227338,19sleep30-21swapper/307:06:353
1068726839,26sleep10-21swapper/107:06:171
926426040,16sleep00-21swapper/007:05:170
1073126042,15sleep20-21swapper/207:06:472
1117699472,35cyclictest0-21swapper/211:36:292
1116799479,13cyclictest0-21swapper/010:27:420
11167994610,25cyclictest0-21swapper/010:36:290
11168994514,20cyclictest0-21swapper/111:20:101
11168994511,24cyclictest0-21swapper/110:48:091
11168994511,24cyclictest0-21swapper/110:48:091
11168994414,19cyclictest0-21swapper/110:55:101
11168994414,15cyclictest0-21swapper/111:43:281
11167994413,18cyclictest0-21swapper/009:10:430
11176994310,22cyclictest0-21swapper/212:26:062
11168994311,15cyclictest0-21swapper/112:37:361
1116799436,26cyclictest0-21swapper/011:31:250
1116799429,23cyclictest0-21swapper/009:17:240
1117699415,29cyclictest0-21swapper/207:55:062
1117699413,30cyclictest0-21swapper/207:10:432
11176994111,19cyclictest0-21swapper/210:00:442
11176994110,22cyclictest0-21swapper/210:38:512
11168994110,21cyclictest0-21swapper/110:32:251
1116799419,22cyclictest0-21swapper/011:18:590
11167994114,24cyclictest0-21swapper/009:44:170
1117699409,21cyclictest0-21swapper/212:00:262
1117699408,21cyclictest0-21swapper/212:36:392
1117699407,22cyclictest0-21swapper/210:10:232
1117699407,22cyclictest0-21swapper/210:10:222
1117699407,22cyclictest0-21swapper/209:31:072
11176994024,13cyclictest0-21swapper/212:23:402
1116899407,16cyclictest0-21swapper/110:02:431
11168994015,16cyclictest0-21swapper/109:57:001
11168994015,15cyclictest0-21swapper/111:35:061
11168994014,16cyclictest0-21swapper/112:25:211
11168994013,17cyclictest0-21swapper/112:08:121
11168994012,18cyclictest0-21swapper/110:54:141
11168994010,21cyclictest0-21swapper/110:15:431
1116799407,23cyclictest0-21swapper/011:08:110
1116799407,23cyclictest0-21swapper/011:08:110
1117699399,21cyclictest0-21swapper/212:18:482
1117699399,21cyclictest0-21swapper/212:18:482
1117699396,24cyclictest0-21swapper/208:15:112
1117699396,24cyclictest0-21swapper/208:15:112
1117699395,22cyclictest0-21swapper/209:03:352
11176993919,17cyclictest0-21swapper/209:10:412
11176993915,14cyclictest0-21swapper/209:24:342
1116899399,20cyclictest0-21swapper/110:44:581
11168993925,12cyclictest0-21swapper/111:52:491
11168993914,23cyclictest0-21swapper/109:52:321
11168993914,15cyclictest0-21swapper/110:37:081
11167993913,23cyclictest0-21swapper/012:12:540
11167993913,23cyclictest0-21swapper/012:12:540
11167993910,19cyclictest0-21swapper/012:25:500
11180993810,25cyclictest0-21swapper/307:40:393
1117699389,20cyclictest0-21swapper/210:07:482
1117699389,20cyclictest0-21swapper/210:07:482
1117699386,22cyclictest0-21swapper/210:56:152
1117699385,23cyclictest0-21swapper/207:31:562
11176993824,12cyclictest0-21swapper/209:16:062
1117699382,28cyclictest0-21swapper/209:55:282
11176993822,13cyclictest0-21swapper/211:03:542
11176993821,15cyclictest0-21swapper/212:05:332
11176993821,14cyclictest0-21swapper/211:54:292
11176993820,15cyclictest0-21swapper/209:45:342
11176993820,15cyclictest0-21swapper/209:37:342
11176993820,15cyclictest0-21swapper/209:37:342
11176993817,18cyclictest0-21swapper/210:31:092
11168993816,19cyclictest0-21swapper/109:34:351
11168993815,21cyclictest0-21swapper/109:48:091
11168993814,13cyclictest0-21swapper/112:20:311
11168993813,22cyclictest0-21swapper/111:08:551
11168993813,22cyclictest0-21swapper/111:08:551
11168993813,13cyclictest0-21swapper/109:22:581
11168993812,15cyclictest0-21swapper/111:27:301
11168993811,17cyclictest0-21swapper/112:00:391
11168993810,19cyclictest0-21swapper/109:37:451
11168993810,19cyclictest0-21swapper/109:37:451
11168993810,18cyclictest0-21swapper/111:15:241
1116799388,22cyclictest0-21swapper/008:55:230
1116799388,17cyclictest0-21swapper/010:14:030
1116799388,17cyclictest0-21swapper/010:14:030
11167993819,5cyclictest81rcu_preempt11:43:360
11167993814,22cyclictest0-21swapper/009:46:400
11167993813,22cyclictest0-21swapper/010:06:260
11167993813,22cyclictest0-21swapper/010:06:260
11167993810,12cyclictest0-21swapper/009:28:500
1118099377,16cyclictest0-21swapper/309:17:593
11180993711,24cyclictest0-21swapper/309:42:263
1117699376,21cyclictest0-21swapper/207:15:292
1117699375,22cyclictest0-21swapper/209:54:202
11176993723,11cyclictest0-21swapper/210:46:502
11176993723,11cyclictest0-21swapper/210:46:502
1117699372,27cyclictest0-21swapper/208:29:302
11176993722,12cyclictest0-21swapper/210:53:452
11176993721,14cyclictest0-21swapper/210:44:172
11176993718,16cyclictest0-21swapper/210:23:092
11176993711,16cyclictest0-21swapper/209:44:582
11168993716,19cyclictest0-21swapper/110:29:471
11168993715,20cyclictest0-21swapper/110:06:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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