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2023-03-24 - 16:41

x86 Intel (undisclosed) @1600 MHz, Linux 4.9.20-rt16 (Profile)

Latency plot of system in rack #7, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack7slot1.osadl.org (updated Fri Mar 24, 2023 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13734211654,23sleep10-21swapper/107:09:011
13430211355,22sleep20-21swapper/207:05:492
13779211251,23sleep30-21swapper/307:09:323
313712870,3sleep312938-21stress09:45:023
163472870,1sleep216349-21unixbench_multi10:15:472
1361228152,24sleep00-21swapper/007:07:440
166552720,1sleep012938-21stress10:17:350
1395899667,48cyclictest0-21swapper/111:40:381
1395899656,43cyclictest0-21swapper/111:10:401
1395899655,50cyclictest0-21swapper/109:55:451
1395899655,50cyclictest0-21swapper/109:55:451
1395899645,43cyclictest0-21swapper/109:50:381
1395899645,43cyclictest0-21swapper/109:50:381
1395899637,41cyclictest0-21swapper/112:15:431
1395899636,43cyclictest0-21swapper/111:20:371
1395899633,49cyclictest0-21swapper/111:53:061
1395899626,38cyclictest0-21swapper/109:45:501
1395899625,46cyclictest0-21swapper/109:30:311
1395899616,45cyclictest0-21swapper/110:35:001
1395899616,45cyclictest0-21swapper/110:35:001
1395899616,40cyclictest0-21swapper/111:15:191
1395899616,39cyclictest0-21swapper/112:40:011
1395899606,44cyclictest0-21swapper/112:20:181
1395899606,44cyclictest0-21swapper/112:20:171
1395899606,43cyclictest0-21swapper/110:50:391
1395899606,39cyclictest0-21swapper/110:15:291
1395899606,38cyclictest0-21swapper/109:10:311
1395899605,43cyclictest0-21swapper/110:40:321
1395899605,16cyclictest0-21swapper/111:35:291
1395899605,16cyclictest0-21swapper/111:35:281
1395899596,43cyclictest0-21swapper/112:25:361
1395899596,42cyclictest0-21swapper/111:05:221
1395899596,42cyclictest0-21swapper/111:05:211
1395899596,41cyclictest0-21swapper/112:05:311
1395899596,41cyclictest0-21swapper/112:00:201
1395899596,38cyclictest0-21swapper/110:25:341
1395899596,38cyclictest0-21swapper/109:17:051
1395899596,38cyclictest0-21swapper/109:17:051
1395899595,34cyclictest0-21swapper/111:55:351
1395899586,42cyclictest0-21swapper/110:35:381
1395899586,38cyclictest0-21swapper/110:00:171
1395899586,38cyclictest0-21swapper/110:00:161
1395899585,42cyclictest0-21swapper/111:30:131
13958995810,37cyclictest0-21swapper/112:30:241
1395899569,32cyclictest0-21swapper/111:25:411
1395899566,39cyclictest0-21swapper/110:45:271
1395899566,39cyclictest0-21swapper/110:20:211
1395899565,37cyclictest0-21swapper/110:10:461
1395899565,16cyclictest0-21swapper/110:10:001
1395899556,33cyclictest0-21swapper/109:25:441
1395899545,39cyclictest0-21swapper/109:40:191
1395899545,23cyclictest0-21swapper/109:25:011
13957995117,23cyclictest0-21swapper/012:25:250
1395899496,40cyclictest0-21swapper/109:37:121
1395899486,18cyclictest0-21swapper/110:55:491
1395899485,16cyclictest0-21swapper/107:45:321
1395899478,17cyclictest0-21swapper/107:35:171
1395899476,23cyclictest0-21swapper/111:45:371
1395899475,26cyclictest0-21swapper/108:17:361
1395899475,15cyclictest0-21swapper/109:01:351
1395899467,15cyclictest0-21swapper/108:20:091
1395899466,18cyclictest0-21swapper/111:00:331
1395899465,25cyclictest0-21swapper/109:09:151
1395899465,25cyclictest0-21swapper/107:12:561
1395899455,38cyclictest0-21swapper/107:42:151
1395899455,16cyclictest0-21swapper/108:40:101
1395899449,18cyclictest0-21swapper/108:50:231
1395899445,17cyclictest0-21swapper/108:05:481
1395899445,16cyclictest0-21swapper/108:26:141
1395899445,14cyclictest0-21swapper/107:51:361
13957994414,12cyclictest0-21swapper/011:00:240
1396099430,33cyclictest0-21swapper/309:30:143
1395899436,17cyclictest0-21swapper/108:00:091
1395899435,36cyclictest0-21swapper/108:33:101
1395899435,36cyclictest0-21swapper/108:33:091
1395899435,36cyclictest0-21swapper/107:28:351
1395899435,16cyclictest0-21swapper/108:45:331
1395899435,16cyclictest0-21swapper/107:31:131
1395899435,16cyclictest0-21swapper/107:17:071
1395899425,35cyclictest0-21swapper/108:55:121
1395899425,34cyclictest0-21swapper/112:10:141
1395899425,19cyclictest0-21swapper/107:55:041
1395899425,16cyclictest0-21swapper/107:20:571
1395899424,16cyclictest0-21swapper/108:12:101
1395899415,15cyclictest0-21swapper/108:35:041
16632405,14sleep20-21swapper/208:45:342
13957994015,16cyclictest0-21swapper/010:45:510
134032405,14sleep30-21swapper/308:05:443
256482395,13sleep20-21swapper/207:30:042
1395799394,33cyclictest0-21swapper/009:34:460
117532395,15sleep20-21swapper/209:05:252
109812393,14sleep20-21swapper/208:02:592
1395799387,22cyclictest0-21swapper/009:55:430
1395799387,22cyclictest0-21swapper/009:55:430
13957993813,22cyclictest0-21swapper/011:45:580
13957993811,24cyclictest0-21swapper/012:39:250
9702375,11sleep00-21swapper/007:45:160
72502375,14sleep20-21swapper/208:56:342
5742374,13sleep20-21swapper/207:44:332
21872373,13sleep00-21swapper/008:49:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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