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2021-10-24 - 02:45

(undisclosed), Linux 4.9.20-rt16 (Profile)

Latency plot of system in rack #7, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Sun Oct 24, 2021 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8624212160,20sleep20-21swapper/219:05:432
8637211150,55sleep30-21swapper/319:05:533
8829210951,20sleep00-21swapper/019:08:140
891328557,23sleep10-21swapper/119:09:201
128952550,1sleep331569-21stress00:03:533
906899483,29cyclictest31567-21stress22:10:451
906899454,38cyclictest0-21swapper/123:59:571
906899454,38cyclictest0-21swapper/123:59:571
906899454,26cyclictest31567-21stress23:12:481
906899446,24cyclictest0-21swapper/122:15:301
906899443,30cyclictest29749-21cat21:05:171
906899443,26cyclictest31569-21stress21:20:321
906899443,26cyclictest12028-21aten2_r7power_p22:50:151
906899443,22cyclictest14139-21smart_sda21:40:431
906899442,32cyclictest31569-21stress23:05:141
9068994416,15cyclictest0-21swapper/122:40:231
9068994416,15cyclictest0-21swapper/122:40:231
906899433,28cyclictest31077-21if_eth019:55:221
906899433,25cyclictest31567-21stress22:45:191
906899433,23cyclictest31569-21stress21:25:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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