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2026-02-12 - 02:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Wed Feb 11, 2026 12:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19206211754,23sleep20-21swapper/207:07:202
19382211553,24sleep00-21swapper/007:09:350
19145211250,57sleep30-21swapper/307:06:333
19398210445,54sleep10-21swapper/107:09:491
1951299499,26cyclictest0-21swapper/111:25:251
1951299485,29cyclictest0-21swapper/109:25:311
19512994730,15cyclictest0-21swapper/110:31:111
19514994632,12cyclictest0-21swapper/311:18:053
1951299468,28cyclictest0-21swapper/111:38:411
1951299468,27cyclictest0-21swapper/111:10:351
1951299468,26cyclictest0-21swapper/111:55:311
1951299465,29cyclictest0-21swapper/111:30:311
1951299465,29cyclictest0-21swapper/111:30:311
19512994628,16cyclictest0-21swapper/110:27:461
19512994628,16cyclictest0-21swapper/110:27:461
1951299458,23cyclictest0-21swapper/112:00:191
19514994428,13cyclictest0-21swapper/312:08:083
1951299447,27cyclictest0-21swapper/109:40:331
1951299445,20cyclictest0-21swapper/112:10:341
1951299445,20cyclictest0-21swapper/112:10:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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