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2022-10-03 - 14:30

x86 Intel (undisclosed) @1600 MHz, Linux 4.9.20-rt16 (Profile)

Latency plot of system in rack #7, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Mon Oct 03, 2022 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14256211857,56sleep20-21swapper/207:07:352
14398211250,57sleep10-21swapper/107:09:141
14134211250,23sleep30-21swapper/307:06:153
1325928451,27sleep00-21swapper/007:05:240
118152700,1sleep310192-21stress11:21:143
118152700,1sleep310192-21stress11:21:143
161762650,2chrt16178-21missed_timers10:25:303
43602630,1sleep210189-21stress12:14:062
46312590,1sleep310192-21stress10:01:383
14593994314,16cyclictest0-21swapper/110:14:261
43992420,1sleep310189-21stress11:06:433
1459399429,19cyclictest0-21swapper/109:42:481
14593994110,28cyclictest0-21swapper/110:32:021
14594994010,27cyclictest0-21swapper/211:56:312
14593994016,21cyclictest0-21swapper/109:53:341
14592994010,27cyclictest0-21swapper/011:00:130
14594993914,22cyclictest0-21swapper/210:23:292
14594993911,19cyclictest0-21swapper/210:36:462
14593993915,21cyclictest0-21swapper/110:16:351
14593993912,12cyclictest0-21swapper/111:36:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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