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2025-04-26 - 10:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Sat Apr 26, 2025 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11699211653,58sleep10-21swapper/119:06:571
11563211451,21sleep30-21swapper/319:05:263
11778211150,23sleep00-21swapper/019:07:520
1173729469,20sleep20-21swapper/219:07:222
12050995815,40cyclictest0-21swapper/222:30:342
12050995813,25cyclictest0-21swapper/200:25:542
12050995813,25cyclictest0-21swapper/200:25:542
12050995612,41cyclictest0-21swapper/221:50:032
12050995612,20cyclictest0-21swapper/200:15:062
12050995611,42cyclictest0-21swapper/221:48:262
1205199559,28cyclictest0-21swapper/300:32:393
1205199559,28cyclictest0-21swapper/300:32:393
12050995516,18cyclictest0-21swapper/223:45:342
12050995516,15cyclictest0-21swapper/223:53:212
12050995516,15cyclictest0-21swapper/222:16:482
12051995310,24cyclictest0-21swapper/321:59:543
12050995316,17cyclictest0-21swapper/221:57:322
12050995315,15cyclictest0-21swapper/223:42:262
12050995312,17cyclictest0-21swapper/200:30:052
12050995312,17cyclictest0-21swapper/200:30:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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