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2024-04-14 - 23:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Sun Apr 14, 2024 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2397211453,56sleep30-21swapper/307:09:543
2111211453,20sleep10-21swapper/107:07:271
2344211252,55sleep00-21swapper/007:09:280
229129350,38sleep20-21swapper/207:09:052
5582450,1sleep39744-21stress09:48:483
2582994118,20cyclictest0-21swapper/311:09:253
270072405,13sleep20-21swapper/207:47:532
2582994026,12cyclictest0-21swapper/309:54:143
2582994026,12cyclictest0-21swapper/309:54:143
2582994025,13cyclictest0-21swapper/309:27:253
306192395,10sleep20-21swapper/208:50:022
301362395,13sleep20-21swapper/208:48:452
2581993912,24cyclictest0-21swapper/209:23:272
2581993912,24cyclictest0-21swapper/209:23:272
2578993917,20cyclictest0-21swapper/007:49:450
2578993911,21cyclictest0-21swapper/008:15:300
94122385,10sleep20-21swapper/207:19:212
6182385,13sleep10-21swapper/108:54:391
301922385,12sleep20-21swapper/207:54:552
2582993823,12cyclictest0-21swapper/310:03:463
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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