You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-12 - 12:55
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Sat Jul 12, 2025 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21937211552,57sleep00-21swapper/019:09:580
20086211453,23sleep20-21swapper/219:05:062
2540621100,1sleep38805-21stress21:46:243
2540621100,1sleep38805-21stress21:46:243
21851210550,51sleep10-21swapper/119:08:541
1068321020,1sleep18807-21stress21:12:251
2177129567,23sleep30-21swapper/319:07:523
22035995815,32cyclictest0-21swapper/122:35:131
22034995623,21cyclictest0-21swapper/023:25:160
22034995623,21cyclictest0-21swapper/023:25:150
22034995523,21cyclictest0-21swapper/023:05:160
248822530,1sleep08805-21stress23:03:350
2203599513,36cyclictest8805-21stress23:20:141
2203599513,27cyclictest8807-21stress23:28:101
2203599513,27cyclictest8807-21stress23:28:101
22037995016,15cyclictest0-21swapper/300:15:253
22037995015,19cyclictest0-21swapper/319:40:163
2203599503,35cyclictest8805-21stress23:58:421
2203599503,33cyclictest26594-21timerwakeupswit23:05:321
2203599503,28cyclictest8805-21stress23:15:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional