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2024-12-11 - 14:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Wed Dec 11, 2024 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15688211351,57sleep20-21swapper/207:09:492
15615211353,55sleep10-21swapper/107:08:521
15429211050,21sleep00-21swapper/007:06:330
1566428863,20sleep30-21swapper/307:09:303
182592560,1sleep03505-21stress10:57:250
182592560,1sleep03505-21stress10:57:250
49822460,1sleep33508-21stress09:10:323
49822460,1sleep33508-21stress09:10:323
15806994315,25cyclictest0-21swapper/110:10:191
15806994226,14cyclictest0-21swapper/109:40:481
15806994226,14cyclictest0-21swapper/109:40:481
15806994113,25cyclictest0-21swapper/111:30:471
15806994111,27cyclictest0-21swapper/112:19:211
15806994015,22cyclictest0-21swapper/111:51:361
15806993916,21cyclictest0-21swapper/111:00:321
15806993916,20cyclictest0-21swapper/112:35:161
15806993915,22cyclictest0-21swapper/112:33:541
15806993915,21cyclictest0-21swapper/110:40:441
15806993915,15cyclictest0-21swapper/109:10:071
15806993915,15cyclictest0-21swapper/109:10:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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