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2023-05-28 - 02:53

x86 Intel (undisclosed) @1600 MHz, Linux 4.9.20-rt16 (Profile)

Latency plot of system in rack #7, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Sun May 28, 2023 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11917212058,56sleep20-21swapper/219:05:332
12092211152,54sleep00-21swapper/019:07:090
11997210850,53sleep10-21swapper/119:06:121
12180210651,50sleep30-21swapper/319:08:073
28442700,1sleep012568-21stress23:54:330
28442700,1sleep012568-21stress23:54:330
12484996715,41cyclictest0-21swapper/222:40:302
12484996715,41cyclictest0-21swapper/222:40:302
12484996610,45cyclictest0-21swapper/221:50:452
247532650,1sleep112568-21stress23:34:141
12484996016,41cyclictest0-21swapper/221:35:362
12484995614,38cyclictest0-21swapper/222:10:442
12485995512,21cyclictest0-21swapper/323:05:223
12484995511,17cyclictest0-21swapper/223:45:492
1248499537,43cyclictest0-21swapper/223:05:052
1248499529,24cyclictest0-21swapper/200:04:472
1248499527,24cyclictest0-21swapper/223:25:342
1248499527,19cyclictest0-21swapper/200:10:252
1248499525,21cyclictest0-21swapper/220:30:012
12484995215,15cyclictest0-21swapper/223:00:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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