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2026-01-15 - 06:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Thu Jan 15, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20089212156,59sleep30-21swapper/319:08:333
19933212059,21sleep20-21swapper/219:06:322
18373211450,58sleep10-21swapper/119:05:101
19886210850,53sleep00-21swapper/019:05:530
35352415,13sleep30-21swapper/319:45:023
20309994011,20cyclictest0-21swapper/020:45:330
2030999396,22cyclictest0-21swapper/019:35:210
20309993911,19cyclictest0-21swapper/019:15:060
95692385,13sleep20-21swapper/219:59:012
74672385,12sleep30-21swapper/319:54:043
65972385,13sleep30-21swapper/321:08:153
51132385,13sleep20-21swapper/219:45:572
44212385,13sleep00-21swapper/019:45:190
283972385,12sleep30-21swapper/320:42:243
262142385,13sleep30-21swapper/320:36:153
20312993816,19cyclictest0-21swapper/323:56:223
20312993816,19cyclictest0-21swapper/323:56:223
20312993813,22cyclictest0-21swapper/300:35:193
2030999389,20cyclictest0-21swapper/021:02:240
2030999389,20cyclictest0-21swapper/021:02:240
20309993815,20cyclictest0-21swapper/021:42:240
20309993815,20cyclictest0-21swapper/021:42:240
20309993811,17cyclictest0-21swapper/019:23:240
20309993811,17cyclictest0-21swapper/019:12:530
136102385,13sleep20-21swapper/220:06:512
30882375,13sleep20-21swapper/219:42:122
291512375,12sleep30-21swapper/319:26:463
290562375,13sleep10-21swapper/119:25:311
261502375,13sleep20-21swapper/220:35:272
241242375,12sleep30-21swapper/320:31:383
22302375,13sleep10-21swapper/120:56:381
222942375,13sleep20-21swapper/219:14:142
2031099375,17cyclictest0-21swapper/100:00:231
2030999379,22cyclictest0-21swapper/020:10:220
2030999375,23cyclictest0-21swapper/019:29:140
20309993723,12cyclictest0-21swapper/000:23:530
20309993711,17cyclictest0-21swapper/020:36:250
179402375,13sleep10-21swapper/120:18:161
117152375,13sleep20-21swapper/220:04:382
115152375,13sleep10-21swapper/120:02:001
325792365,10sleep30-21swapper/320:52:123
31652365,12sleep30-21swapper/319:43:103
313032365,12sleep00-21swapper/019:32:200
264382365,13sleep10-21swapper/120:39:091
24432365,12sleep30-21swapper/320:59:243
243132365,13sleep10-21swapper/120:34:041
24152365,13sleep00-21swapper/020:59:010
20312993616,17cyclictest0-21swapper/321:20:203
20312993614,20cyclictest0-21swapper/323:20:103
20312993614,20cyclictest0-21swapper/300:20:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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