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2023-01-30 - 06:16

x86 Intel (undisclosed) @1600 MHz, Linux 4.9.20-rt16 (Profile)

Latency plot of system in rack #7, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Mon Jan 30, 2023 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24013212057,23sleep10-21swapper/119:07:261
23926211752,59sleep30-21swapper/319:06:273
2408429247,18sleep00-21swapper/019:08:090
2400628358,20sleep20-21swapper/219:07:222
148392600,1sleep222315-21stress00:04:182
24370994515,28cyclictest0-21swapper/021:17:060
115112450,1sleep222317-21stress23:55:402
24370994315,25cyclictest0-21swapper/022:56:290
24370994112,26cyclictest0-21swapper/023:06:260
24370994027,11cyclictest0-21swapper/022:32:120
24370994027,11cyclictest0-21swapper/022:32:110
24370994014,23cyclictest0-21swapper/021:40:220
24370994014,17cyclictest0-21swapper/000:30:540
2437099396,30cyclictest0-21swapper/022:35:200
2437099396,30cyclictest0-21swapper/022:35:200
24370993916,20cyclictest0-21swapper/000:22:000
24370993914,22cyclictest0-21swapper/023:28:030
24370993913,23cyclictest0-21swapper/023:22:560
24370993911,25cyclictest0-21swapper/023:16:550
24370993911,25cyclictest0-21swapper/023:02:410
91692385,13sleep00-21swapper/020:43:300
265142385,13sleep20-21swapper/219:11:152
26272385,13sleep00-21swapper/019:26:020
24370993815,21cyclictest0-21swapper/021:30:440
24370993815,21cyclictest0-21swapper/021:30:430
24370993815,20cyclictest0-21swapper/023:38:500
24370993815,20cyclictest0-21swapper/022:44:480
24370993814,21cyclictest0-21swapper/023:40:080
24370993814,21cyclictest0-21swapper/000:25:140
24370993810,25cyclictest0-21swapper/000:10:270
219242385,13sleep00-21swapper/021:06:450
219242385,13sleep00-21swapper/021:06:440
122692385,13sleep00-21swapper/020:50:090
96122375,13sleep30-21swapper/320:45:023
96122375,13sleep30-21swapper/320:45:013
44522375,13sleep30-21swapper/320:35:043
314722375,13sleep10-21swapper/120:24:551
313692375,12sleep00-21swapper/020:23:420
303092375,13sleep30-21swapper/319:19:073
2437299379,25cyclictest0-21swapper/222:55:042
2437299376,28cyclictest0-21swapper/200:30:002
24372993714,20cyclictest0-21swapper/223:50:582
24372993712,22cyclictest0-21swapper/223:43:272
24370993714,21cyclictest0-21swapper/021:55:410
24370993711,23cyclictest0-21swapper/022:50:010
221762375,13sleep10-21swapper/121:09:351
221762375,13sleep10-21swapper/121:09:351
194672375,13sleep30-21swapper/321:02:553
185452375,13sleep30-21swapper/319:59:533
184062375,13sleep00-21swapper/019:58:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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