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2024-09-07 - 16:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Sat Sep 07, 2024 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32357213068,24sleep10-21swapper/107:09:281
32391211253,20sleep30-21swapper/307:09:543
32346210051,23sleep00-21swapper/007:09:180
3238529065,20sleep20-21swapper/207:09:502
309162520,1sleep219179-21stress10:54:322
32500995124,24cyclictest0-21swapper/109:12:351
32500994924,22cyclictest0-21swapper/109:29:181
32500994823,22cyclictest0-21swapper/112:13:331
32500994822,23cyclictest0-21swapper/112:16:541
32500994424,13cyclictest0-21swapper/112:09:531
32500994322,19cyclictest0-21swapper/110:55:051
32500994224,16cyclictest0-21swapper/110:40:211
3250099416,32cyclictest0-21swapper/111:10:231
32500994124,15cyclictest0-21swapper/111:58:401
32500994124,15cyclictest0-21swapper/110:15:361
3250099407,30cyclictest0-21swapper/109:43:421
3250099405,33cyclictest0-21swapper/112:20:201
3250099405,33cyclictest0-21swapper/112:20:201
32500994017,21cyclictest0-21swapper/111:30:261
32500994017,20cyclictest0-21swapper/109:15:271
3250099397,29cyclictest0-21swapper/110:02:021
3250099394,32cyclictest0-21swapper/109:35:301
32500993923,14cyclictest0-21swapper/112:35:261
32500993923,14cyclictest0-21swapper/112:00:181
32500993923,14cyclictest0-21swapper/109:45:431
32500993922,15cyclictest0-21swapper/110:25:351
111932390,1sleep119177-21stress11:24:431
3250099387,28cyclictest0-21swapper/110:50:281
3250099385,31cyclictest0-21swapper/110:45:491
32500993823,13cyclictest0-21swapper/110:36:021
32500993822,14cyclictest0-21swapper/111:45:271
32500993820,16cyclictest0-21swapper/109:30:281
32499993810,25cyclictest0-21swapper/012:36:260
32501993713,21cyclictest0-21swapper/210:25:322
3250099376,28cyclictest0-21swapper/110:30:161
3250099376,28cyclictest0-21swapper/110:30:161
3250099375,29cyclictest0-21swapper/110:24:011
32500993719,16cyclictest0-21swapper/111:06:251
32500993718,17cyclictest0-21swapper/111:37:421
32500993718,16cyclictest0-21swapper/111:30:011
32500993718,16cyclictest0-21swapper/111:00:311
32500993716,18cyclictest0-21swapper/111:15:221
32500993716,18cyclictest0-21swapper/111:15:221
32499993716,18cyclictest0-21swapper/009:16:330
188502375,13sleep20-21swapper/209:06:552
167412375,13sleep20-21swapper/209:01:462
32500993617,17cyclictest0-21swapper/110:05:271
32500993616,18cyclictest0-21swapper/111:40:251
32500993616,18cyclictest0-21swapper/109:56:081
32500993616,18cyclictest0-21swapper/109:56:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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