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2025-02-19 - 00:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Tue Feb 18, 2025 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18904211553,57sleep10-21swapper/107:09:371
18733211058,48sleep20-21swapper/207:07:362
16734210750,21sleep30-21swapper/307:05:013
266532880,1sleep226655-21grep10:00:332
1879928353,25sleep00-21swapper/007:08:260
222762720,1sleep022273-21egrep11:20:130
222762720,1sleep022273-21egrep11:20:130
19036996213,18cyclictest0-21swapper/110:50:241
268972600,1sleep06293-21stress11:34:530
1903699586,28cyclictest0-21swapper/111:20:141
1903699586,28cyclictest0-21swapper/111:20:141
1903699576,29cyclictest0-21swapper/110:00:191
1903699567,29cyclictest0-21swapper/111:45:541
1903699566,47cyclictest0-21swapper/109:35:291
1903699566,47cyclictest0-21swapper/109:35:291
19036995614,22cyclictest0-21swapper/111:04:321
19036995614,22cyclictest0-21swapper/111:04:321
1903699557,19cyclictest0-21swapper/112:15:341
1903699556,28cyclictest0-21swapper/112:21:261
19036995514,21cyclictest0-21swapper/111:50:071
19036995514,20cyclictest0-21swapper/110:59:161
1903699539,26cyclictest0-21swapper/111:10:131
1903699536,28cyclictest0-21swapper/111:30:071
1903699536,28cyclictest0-21swapper/109:54:291
1903699536,25cyclictest0-21swapper/112:01:391
1903699536,20cyclictest0-21swapper/111:37:011
19036995314,21cyclictest0-21swapper/111:44:511
19036995313,37cyclictest0-21swapper/111:55:161
19036995313,37cyclictest0-21swapper/111:55:151
1903699528,19cyclictest0-21swapper/110:40:331
1903699526,44cyclictest0-21swapper/110:35:271
1903699526,25cyclictest0-21swapper/110:45:191
1903699526,25cyclictest0-21swapper/110:45:181
19036995212,22cyclictest0-21swapper/109:56:301
19036995211,37cyclictest0-21swapper/110:10:151
19036995011,15cyclictest0-21swapper/109:20:271
1903699499,37cyclictest0-21swapper/111:15:041
1903699497,39cyclictest0-21swapper/111:25:041
1903699497,39cyclictest0-21swapper/111:25:031
1903699497,39cyclictest0-21swapper/109:40:311
1903699495,24cyclictest0-21swapper/112:13:011
19036994814,15cyclictest0-21swapper/112:35:251
19036994812,15cyclictest0-21swapper/112:06:151
1903699478,19cyclictest0-21swapper/112:28:151
1903699478,18cyclictest0-21swapper/109:30:311
1903699478,18cyclictest0-21swapper/109:30:301
1903699476,22cyclictest0-21swapper/109:15:341
1903699476,18cyclictest0-21swapper/110:20:191
19036994711,16cyclictest0-21swapper/111:10:011
1903699465,24cyclictest0-21swapper/108:53:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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