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2024-04-23 - 10:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Tue Apr 23, 2024 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20275211956,56sleep20-21swapper/219:09:562
19939211553,56sleep30-21swapper/319:06:393
20130210951,20sleep00-21swapper/019:08:380
20062210449,50sleep10-21swapper/119:07:491
20426994833,12cyclictest0-21swapper/021:55:400
20426994815,21cyclictest27743-21stress23:41:110
20426994731,13cyclictest0-21swapper/000:16:010
20426994630,13cyclictest0-21swapper/022:42:350
20426994630,13cyclictest0-21swapper/022:42:350
2042699457,31cyclictest0-21swapper/019:25:260
2042699457,24cyclictest0-21swapper/022:45:170
20426994530,13cyclictest0-21swapper/023:20:320
20426994530,13cyclictest0-21swapper/000:05:010
20426994410,25cyclictest0-21swapper/023:35:390
2042699437,25cyclictest0-21swapper/022:33:290
20426994334,7cyclictest27743-21stress23:45:320
20426994329,12cyclictest0-21swapper/000:05:310
20426994325,16cyclictest0-21swapper/021:30:310
20426994325,15cyclictest0-21swapper/021:25:200
20426994318,13cyclictest27743-21stress21:10:180
20426994310,23cyclictest0-21swapper/022:10:320
20426994228,12cyclictest0-21swapper/022:23:200
20426994227,13cyclictest0-21swapper/000:20:400
20426994225,15cyclictest0-21swapper/022:28:240
20426994225,15cyclictest0-21swapper/021:35:340
20426994212,13cyclictest27743-21stress22:55:390
20426994127,12cyclictest0-21swapper/021:20:150
20426994126,13cyclictest0-21swapper/023:11:020
20427994016,22cyclictest0-21swapper/123:24:481
20426994030,8cyclictest27743-21stress23:15:430
20426994030,8cyclictest27743-21stress23:15:420
20426994026,12cyclictest0-21swapper/023:25:190
20426994026,12cyclictest0-21swapper/022:05:180
20426994026,12cyclictest0-21swapper/022:05:180
20426994026,12cyclictest0-21swapper/022:00:280
20426994026,12cyclictest0-21swapper/022:00:280
20426994016,14cyclictest14603-21python19:50:270
20426994012,18cyclictest31569-21sh21:15:180
20427993915,21cyclictest0-21swapper/122:01:231
20427993915,21cyclictest0-21swapper/122:01:231
20427993915,21cyclictest0-21swapper/121:28:591
20426993919,15cyclictest0-21swapper/020:15:310
20426993918,15cyclictest0-21swapper/020:55:120
20426993916,8cyclictest27741-21stress00:28:260
20426993916,8cyclictest27741-21stress00:28:260
20426993910,12cyclictest27743-21stress21:45:380
20427993813,23cyclictest0-21swapper/121:40:331
20426993823,13cyclictest0-21swapper/021:53:110
20426993815,13cyclictest4117-21aten2_r7power_c19:35:100
20426993813,14cyclictest27741-21stress23:05:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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