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2021-06-17 - 19:30

Intel(R) Celeron(R) CPU G1820 @ 2.70GHz, Linux 3.18.40-rt42 (Profile)

Latency plot of system in rack #a, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackaslot8.osadl.org (updated Thu Jun 17, 2021 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2427423315,16sleep10-21swapper/107:06:101
2442822917,11sleep00-21swapper/007:07:480
2470099241,9cyclictest0-21swapper/112:00:001
2470099241,13cyclictest0-21swapper/111:39:591
2469899241,11cyclictest0-21swapper/010:17:000
24700992312,6cyclictest62450irq/31-eth0-rx-10:23:001
2469899230,21cyclictest0-21swapper/012:03:000
2470099221,15cyclictest0-21swapper/112:08:591
2470099210,14cyclictest0-21swapper/109:38:581
2469899211,8cyclictest0-21swapper/007:57:590
2469899210,9cyclictest28055-21ssh09:45:590
2469899210,16cyclictest0-21swapper/007:52:000
2470099205,6cyclictest15916-21ssh09:59:591
24700992018,1cyclictest0-21swapper/108:41:001
2469899200,12cyclictest0-21swapper/008:10:590
2470099190,5cyclictest19125-21ssh11:48:591
2469899193,9cyclictest0-21swapper/010:13:590
24698991918,1cyclictest22055-21kworker/u4:009:26:010
2469899191,2cyclictest0-21swapper/009:37:000
2470099184,5cyclictest0-21swapper/110:27:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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