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2019-07-23 - 11:18

VIA C7 Processor 1000MHz, Linux 2.6.33.14-rt31 (Profile)

Latency plot of system in rack #b, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Characteristics of the 20 highest latencies:
System rackbslot2.osadl.org (updated Fri Jan 25, 2019 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5921994918cyclictest0-21swapper11:30:480
5921994826cyclictest0-21swapper06:37:250
5921994824cyclictest5919-21cyclictest08:37:280
5921994824cyclictest5919-21cyclictest08:35:220
5921994824cyclictest5919-21cyclictest08:16:110
5921994820cyclictest0-21swapper07:47:560
5921994725cyclictest0-21swapper09:50:580
5921994724cyclictest0-21swapper09:06:310
5921994724cyclictest0-21swapper07:18:330
5921994723cyclictest5919-21cyclictest10:51:480
5921994723cyclictest5919-21cyclictest10:41:330
5921994723cyclictest5919-21cyclictest06:58:150
5921994723cyclictest161events/010:30:240
5921994721cyclictest0-21swapper10:03:450
5921994721cyclictest0-21swapper08:56:200
5921994720cyclictest0-21swapper08:20:160
5921994719cyclictest0-21swapper09:23:320
5921994719cyclictest0-21swapper08:25:370
5921994719cyclictest0-21swapper07:12:340
5921994717cyclictest0-21swapper08:27:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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