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2022-12-02 - 01:47

x86 Intel Core i7-950 @3.06 GHz, Linux 2.6.33.7.2-rt30-32 (Profile)

Latency plot of system in rack #b, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100, highest latencies:
System rackbslot5.osadl.org (updated Wed Nov 30, 2022 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2855622423sleep50-21swapper06:25:455
2426222113sleep40-21swapper10:23:214
1537021919sleep70-21swapper11:07:337
1103721917sleep50-21swapper09:55:455
651921817sleep30-21swapper07:46:183
559521817sleep10-21swapper09:44:041
510621817sleep40-21swapper05:39:424
3122421817sleep10-21swapper07:33:121
30921817sleep30-21swapper09:36:143
2891121817sleep70-21swapper10:30:047
2809321817sleep20-21swapper07:24:402
2782421817sleep10-21swapper08:26:181
2484421817sleep10-21swapper09:22:121
2357321817sleep10-21swapper10:20:061
2279521817sleep10-21swapper07:15:031
2012821817sleep10-21swapper07:09:591
189121817sleep40-21swapper10:40:334
1728621817sleep10-21swapper08:07:531
1703421817sleep50-21swapper08:04:215
1691721817sleep50-21swapper09:08:075
1691721817sleep50-21swapper09:08:075
1672321817sleep10-21swapper09:05:231
1672321817sleep10-21swapper09:05:231
1574321817sleep50-21swapper10:07:215
1558121817sleep30-21swapper10:05:033
1255721817sleep30-21swapper11:00:253
1114821817sleep10-21swapper09:57:171
1101821817sleep40-21swapper09:55:284
1056421817sleep10-21swapper05:51:321
1004821817sleep20-21swapper10:57:362
274499172cyclictest1281sirq-hrtimer/009:11:200
274499172cyclictest1281sirq-hrtimer/007:03:250
274499172cyclictest1281sirq-hrtimer/006:35:110
1891721717sleep20-21swapper10:13:262
672721615sleep60-21swapper06:43:476
57921615sleep50-21swapper08:34:385
3042721614sleep50-21swapper08:30:145
274499165cyclictest1281sirq-hrtimer/007:35:210
274499162cyclictest1281sirq-hrtimer/011:03:220
274499162cyclictest1281sirq-hrtimer/010:32:490
274499162cyclictest1281sirq-hrtimer/009:33:310
274499162cyclictest1281sirq-hrtimer/009:33:070
274499162cyclictest1281sirq-hrtimer/009:33:070
274499162cyclictest1281sirq-hrtimer/008:43:320
274499162cyclictest1281sirq-hrtimer/008:04:020
274499162cyclictest1281sirq-hrtimer/006:03:310
274499160cyclictest1281sirq-hrtimer/010:33:100
274499160cyclictest1281sirq-hrtimer/008:27:530
2282621615sleep50-21swapper07:15:315
2276121615sleep60-21swapper07:14:366
1930821615sleep60-21swapper07:08:286
190021615sleep60-21swapper08:38:316
1532121613sleep50-21swapper11:06:515
1321421615sleep20-21swapper05:56:212
122621613sleep50-21swapper07:37:485
981621513sleep50-21swapper10:54:195
932521515sleep70-21swapper09:53:317
824121513sleep50-21swapper09:48:495
725121513sleep50-21swapper10:50:435
687621513sleep50-21swapper06:45:545
570121513sleep50-21swapper09:45:365
518521513sleep50-21swapper05:40:485
420921513sleep50-21swapper06:40:505
340621513sleep50-21swapper08:40:225
317621513sleep40-21swapper09:42:314
3150121513sleep50-21swapper10:34:025
3074421513sleep50-21swapper07:29:155
2999921513sleep50-21swapper09:29:365
2999921513sleep50-21swapper09:29:365
2879521513sleep50-21swapper10:28:345
2823221513sleep50-21swapper07:26:355
2789721514sleep50-21swapper08:27:185
274499154cyclictest1281sirq-hrtimer/009:07:220
274499154cyclictest1281sirq-hrtimer/009:07:220
274499152cyclictest1281sirq-hrtimer/010:58:200
274499152cyclictest1281sirq-hrtimer/010:50:080
274499152cyclictest1281sirq-hrtimer/010:08:250
274499152cyclictest1281sirq-hrtimer/009:56:540
274499152cyclictest1281sirq-hrtimer/009:43:500
274499152cyclictest1281sirq-hrtimer/009:42:140
274499152cyclictest1281sirq-hrtimer/009:27:450
274499152cyclictest1281sirq-hrtimer/008:21:050
274499152cyclictest1281sirq-hrtimer/008:08:480
274499152cyclictest1281sirq-hrtimer/007:32:060
274499152cyclictest1281sirq-hrtimer/007:13:390
274499152cyclictest1281sirq-hrtimer/006:58:320
274499152cyclictest1281sirq-hrtimer/006:38:280
274499152cyclictest1281sirq-hrtimer/006:29:220
274499152cyclictest1281sirq-hrtimer/006:23:270
274499152cyclictest1281sirq-hrtimer/006:01:520
274499152cyclictest1281sirq-hrtimer/005:57:340
274499152cyclictest1281sirq-hrtimer/005:50:290
2744991513cyclictest0-21swapper07:43:210
274499151cyclictest1281sirq-hrtimer/010:54:420
274499151cyclictest1281sirq-hrtimer/010:07:270
274499151cyclictest1281sirq-hrtimer/008:59:360
274499151cyclictest1281sirq-hrtimer/008:13:410
274499150cyclictest1281sirq-hrtimer/010:23:280
274499150cyclictest1281sirq-hrtimer/010:13:240
274499150cyclictest1281sirq-hrtimer/006:15:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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