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2026-01-20 - 06:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Jan 20, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1473821710,6sleep72476799cyclictest23:09:1413
241812139116,17sleep30-21swapper/319:09:199
2907921250,1sleep00-21swapper/023:26:300
1364221210,3sleep513647-21run-parts22:49:4111
241802120104,11sleep20-21swapper/219:09:188
240112120104,12sleep150-21swapper/1519:07:067
1268921180,1sleep50-21swapper/523:37:3311
241902115103,8sleep120-21swapper/1219:09:284
24293211392,16sleep90-21swapper/919:10:1315
1983121120,0sleep150-21swapper/1522:50:237
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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