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2025-07-13 - 10:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Jul 13, 2025 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2625321470,6sleep12825699cyclictest23:54:384
672521400,1sleep156726-21systemd-cgroups21:52:277
672521400,1sleep156726-21systemd-cgroups21:52:277
3157221350,0sleep110-21swapper/1121:51:353
3157221350,0sleep110-21swapper/1121:51:353
1217921260,1sleep50-21swapper/522:40:2611
76662124104,16sleep40-21swapper/419:09:1010
371221210,1sleep100-21swapper/1021:20:002
75922118104,8sleep120-21swapper/1219:08:144
3250621120,1sleep140-21swapper/1422:28:006
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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