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2023-12-08 - 23:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri Dec 08, 2023 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
322121750,5sleep142188099cyclictest22:48:036
322121750,5sleep142188099cyclictest22:48:036
1417321360,0sleep140-21swapper/1400:25:086
692821330,0sleep60-21swapper/621:23:2412
211732133104,24sleep140-21swapper/1419:07:116
21166212892,31sleep70-21swapper/719:07:0413
21253211292,13sleep30-21swapper/319:08:049
1215521110,1sleep10-21swapper/100:20:221
3012321040,1sleep00-21swapper/022:30:100
2233121040,1sleep30-21swapper/319:45:459
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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