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2024-04-15 - 20:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon Apr 15, 2024 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1982921710,7sleep31942999cyclictest21:39:329
1606521340,5sleep41943199cyclictest22:12:1010
1606521340,5sleep41943199cyclictest22:12:1010
2992921300,1sleep31942999cyclictest23:54:049
188772130104,22sleep130-21swapper/1319:11:505
18783212793,29sleep80-21swapper/819:11:1314
18521211892,21sleep50-21swapper/519:07:4111
186182116102,9sleep100-21swapper/1019:08:512
18620211595,16sleep120-21swapper/1219:08:534
2366321100,0sleep50-21swapper/523:16:0711
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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