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2024-07-27 - 03:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri Jul 26, 2024 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1659621430,0sleep60-21swapper/622:59:0712
24676211892,22sleep150-21swapper/1519:10:397
24676211892,22sleep150-21swapper/1519:10:397
24824211596,14sleep130-21swapper/1319:12:455
24824211596,14sleep130-21swapper/1319:12:455
24675211092,13sleep140-21swapper/1419:10:386
24675211092,13sleep140-21swapper/1419:10:386
24600210980,24sleep120-21swapper/1219:09:324
24600210980,24sleep120-21swapper/1219:09:324
23665210995,6sleep60-21swapper/619:08:5312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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