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2025-05-23 - 09:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri May 23, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290112134103,26sleep50-21swapper/519:17:0711
2594821340,14sleep140-21swapper/1419:13:146
280962129102,22sleep100-21swapper/1019:14:152
786221270,3sleep132957799cyclictest21:33:205
289242126111,9sleep110-21swapper/1119:15:523
1608521170,0sleep00-21swapper/021:55:030
831721070,4sleep52956599cyclictest23:36:4611
831721070,4sleep52956599cyclictest23:36:4611
28981210491,9sleep120-21swapper/1219:16:424
234162990,2sleep10-21swapper/123:49:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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