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2026-06-11 - 06:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Thu Jun 11, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
192221320,1sleep81777399cyclictest22:52:5314
17323211995,20sleep130-21swapper/1319:12:215
170972118104,9sleep100-21swapper/1019:09:542
758821170,6sleep558-21ksoftirqd/522:30:3811
3166121170,4sleep71776999cyclictest00:11:4613
2412621170,0sleep130-21swapper/1321:15:525
2412621170,0sleep130-21swapper/1321:15:525
2146021150,3sleep1021459-21run-parts23:23:562
1503321150,6sleep141778099cyclictest22:40:566
2235821140,1sleep40-21swapper/423:59:5610
2235821140,1sleep40-21swapper/423:59:5610
2257821130,6sleep141778099cyclictest21:56:336
1512821120,3sleep111777699cyclictest21:55:413
16891211181,24sleep10-21swapper/119:08:091
17066210883,21sleep140-21swapper/1419:09:266
17335210792,9sleep80-21swapper/819:12:3214
17137210691,11sleep110-21swapper/1119:10:273
17138210491,9sleep120-21swapper/1219:10:284
1024621040,0sleep30-21swapper/323:13:079
2529821030,0sleep20-21swapper/221:25:038
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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