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2025-07-05 - 18:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Sat Jul 05, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311562140122,14sleep140-21swapper/1419:10:186
579621350,0sleep80-21swapper/823:19:2514
579621350,0sleep80-21swapper/823:19:2514
310052134120,8sleep80-21swapper/819:08:5114
2974821330,0sleep130-21swapper/1322:02:285
310282129106,19sleep100-21swapper/1019:09:092
310682125107,14sleep130-21swapper/1319:09:455
30862211891,22sleep90-21swapper/919:07:0015
890921160,1sleep90-21swapper/922:36:0615
308152116103,8sleep20-21swapper/219:06:218
267421150,4sleep53158599cyclictest23:33:1711
30997210991,14sleep00-21swapper/019:08:430
1439221080,1sleep1514390-21sshd22:33:167
30965210691,11sleep40-21swapper/419:08:1510
1645921060,0sleep50-21swapper/521:29:2611
31132210593,6sleep70-21swapper/719:09:5513
30806210591,9sleep110-21swapper/1119:06:143
30973210491,9sleep120-21swapper/1219:08:234
30966210492,6sleep50-21swapper/519:08:1611
2091621040,1sleep20-21swapper/222:12:278
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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