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2024-09-16 - 04:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Mon Sep 16, 2024 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149802130102,24sleep20-21swapper/219:12:088
117032126106,16sleep120-21swapper/1219:09:214
149282121105,12sleep60-21swapper/619:11:2312
150292120100,15sleep130-21swapper/1319:12:515
149192117104,9sleep140-21swapper/1419:11:156
15042211493,16sleep90-21swapper/919:13:0315
2978221120,1sleep110-21swapper/1122:22:563
2244721100,3sleep41563099cyclictest21:45:2210
15180211092,11sleep10-21swapper/119:14:151
14836210891,9sleep30-21swapper/319:10:169
15023210692,10sleep70-21swapper/719:12:4513
14948210491,8sleep50-21swapper/519:11:3811
1407321020,1sleep151371ktimersoftd/1522:37:267
474321010,1sleep80-21swapper/800:28:3514
3027721000,1sleep90-21swapper/900:01:1915
288932980,4sleep111563999cyclictest22:51:333
288932980,4sleep111563999cyclictest22:51:333
262332970,1sleep00-21swapper/022:34:470
209642970,3sleep931423-1kworker/9:0H00:34:2915
186922960,0sleep60-21swapper/623:47:5412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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