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2025-06-17 - 06:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Tue Jun 17, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2138021850,2sleep31882599cyclictest00:12:539
2850721480,3sleep928505-21cp23:32:3515
182632126103,18sleep10-21swapper/119:09:201
18364212089,26sleep100-21swapper/1019:10:012
180332119103,11sleep110-21swapper/1119:06:173
18354211789,22sleep40-21swapper/419:09:5510
1218821170,27sleep10-21swapper/121:43:361
182742116103,9sleep90-21swapper/919:09:2815
2724121110,1sleep111051ktimersoftd/1122:06:303
2724121110,1sleep111051ktimersoftd/1122:06:303
1892821110,6sleep101883699cyclictest22:30:332
1100321060,4sleep101883699cyclictest20:15:462
3077021050,0sleep150-21swapper/1521:45:427
2593121050,6sleep141884299cyclictest21:37:566
836521020,2sleep449-21ksoftirqd/421:12:0510
11390991000,84rtkit-daemon0-21swapper/619:06:4112
197002990,2sleep1119699-21bash21:44:343
197272980,1sleep00-21swapper/023:38:510
55582960,0sleep90-21swapper/921:25:3315
1798229676,14sleep00-21swapper/019:05:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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