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2021-10-24 - 01:56

Intel(R) Xeon(R) CPU E5620 @ 2.40GHz, Linux 4.19.127-rt55 (Profile)

Latency plot of system in rack #c, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Fri Oct 15, 2021 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2103821780,5sleep82755999cyclictest21:43:2214
1428121400,4sleep52755499cyclictest23:26:0211
269752133103,25sleep50-21swapper/519:12:3011
2461521310,0sleep10-21swapper/121:36:011
270742122102,16sleep150-21swapper/1519:13:127
26604212092,23sleep110-21swapper/1119:09:073
330221180,0sleep140-21swapper/1400:13:326
330221180,0sleep140-21swapper/1400:13:326
797621170,1sleep02754799cyclictest00:14:060
797621170,1sleep02754799cyclictest00:14:060
793021170,7sleep42755299cyclictest21:22:1010
781721150,7sleep152756999cyclictest21:25:497
269232115102,9sleep120-21swapper/1219:11:494
768821140,1sleep140-21swapper/1422:37:306
971821050,0sleep30-21swapper/321:14:399
26933210573,27sleep30-21swapper/319:11:569
26872210490,9sleep70-21swapper/719:11:1213
1127821020,0sleep50-21swapper/521:54:0111
1127821020,0sleep50-21swapper/521:54:0111
951121010,7sleep112756399cyclictest22:21:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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