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2024-05-29 - 07:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Wed May 29, 2024 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
109842140105,30sleep30-21swapper/319:10:269
109172135105,25sleep100-21swapper/1019:09:292
110232133104,24sleep80-21swapper/819:11:0314
111752125103,17sleep130-21swapper/1319:12:295
110482124104,14sleep110-21swapper/1119:11:223
111652121103,14sleep40-21swapper/419:12:2010
110152118102,12sleep00-21swapper/019:10:550
10979210792,11sleep150-21swapper/1519:10:227
10902210793,10sleep120-21swapper/1219:09:154
10914210695,7sleep70-21swapper/719:09:2613
665721050,5sleep141165099cyclictest00:05:516
2221721020,7sleep71163999cyclictest22:26:3013
2450121010,2sleep80-21swapper/823:52:5514
249402990,1sleep50-21swapper/523:33:5211
249402990,1sleep50-21swapper/523:33:5211
200702980,1sleep110-21swapper/1122:18:333
87822970,4sleep111164799cyclictest22:54:233
230702960,1sleep120-21swapper/1222:11:534
144772960,1sleep70-21swapper/722:58:5213
62242940,1sleep150-21swapper/1521:02:557
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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