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2024-07-27 - 07:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Sat Jul 27, 2024 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1046221870,6sleep12775599cyclictest23:54:091
1046221870,6sleep12775599cyclictest23:54:091
505221730,4sleep42775999cyclictest22:25:5710
2487721650,31sleep00-21swapper/019:08:480
2723121320,4sleep112776899cyclictest23:56:443
2723121320,4sleep112776899cyclictest23:56:443
27051212492,27sleep50-21swapper/519:11:0211
27094212094,21sleep100-21swapper/1019:11:392
270572117104,8sleep90-21swapper/919:11:0615
26251211792,20sleep130-21swapper/1319:09:025
2857421140,1sleep140-21swapper/1423:38:366
2857421140,1sleep140-21swapper/1423:38:366
260021090,1sleep20-21swapper/200:19:038
27079210892,12sleep120-21swapper/1219:11:254
26962210790,8sleep80-21swapper/819:09:4514
3086521050,6sleep142777399cyclictest00:27:486
1315021040,2sleep91-21systemd23:59:0615
1315021040,2sleep91-21systemd23:59:0615
27091210391,7sleep70-21swapper/719:11:3613
1887421020,0sleep50-21swapper/500:15:5311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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