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2021-07-26 - 18:41

Intel(R) Xeon(R) CPU E5620 @ 2.40GHz, Linux 4.19.127-rt55 (Profile)

Latency plot of system in rack #c, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Mon Jul 26, 2021 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304921390,0sleep110-21swapper/1121:33:113
304921390,0sleep110-21swapper/1121:33:113
23495212893,30sleep120-21swapper/1219:08:014
23495212893,30sleep120-21swapper/1219:08:014
23632212092,23sleep30-21swapper/319:09:449
23632212092,23sleep30-21swapper/319:09:449
238582115102,9sleep70-21swapper/719:12:1313
238582115102,9sleep70-21swapper/719:12:1313
23840211391,17sleep100-21swapper/1019:12:002
23840211391,17sleep100-21swapper/1019:12:002
1489421120,4sleep102436499cyclictest21:24:372
1489421120,4sleep102436499cyclictest21:24:372
2201821100,1sleep10-21swapper/123:45:421
2201821100,1sleep10-21swapper/123:45:421
2880921030,6sleep62435899cyclictest21:52:3812
672321020,0sleep70-21swapper/721:18:2513
3244621020,1sleep150-21swapper/1523:14:547
1550221010,1sleep50-21swapper/523:02:2611
23683210080,15sleep150-21swapper/1519:10:287
23683210080,15sleep150-21swapper/1519:10:287
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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