You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-16 - 13:59

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #c, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot3s.osadl.org (updated Sat May 16, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
82622319304,5sleep30-21swapper/319:09:273
79882317308,7sleep10-21swapper/119:05:511
82802315307,5sleep20-21swapper/219:09:382
64762314299,5sleep00-21swapper/019:05:100
8577992990,298cyclictest29235-21kworker/u16:3+efi_rts_wq23:51:123
8575992990,298cyclictest26713-21kworker/u16:1+efi_rts_wq21:45:121
8577992980,297cyclictest9991-21kworker/u16:0+efi_rts_wq00:25:133
8577992980,297cyclictest26713-21kworker/u16:1+efi_rts_wq22:50:103
8574992980,297cyclictest32546-21kworker/u16:2+efi_rts_wq21:09:480
8574992980,297cyclictest32546-21kworker/u16:2+efi_rts_wq20:40:120
8577992961,294cyclictest9991-21kworker/u16:0+efi_rts_wq00:10:103
8576992960,295cyclictest26713-21kworker/u16:1+efi_rts_wq23:00:112
8574992960,295cyclictest32546-21kworker/u16:2+efi_rts_wq20:50:130
8577992950,294cyclictest3878-21kworker/u16:2+efi_rts_wq00:15:123
8575992950,294cyclictest9991-21kworker/u16:0+efi_rts_wq23:35:121
8577992940,293cyclictest26713-21kworker/u16:1+efi_rts_wq20:05:133
8575992940,293cyclictest32546-21kworker/u16:2+efi_rts_wq22:40:141
8575992940,293cyclictest32546-21kworker/u16:2+efi_rts_wq22:40:131
8577992920,291cyclictest26713-21kworker/u16:1+efi_rts_wq22:55:113
8576992920,291cyclictest32546-21kworker/u16:2+efi_rts_wq19:30:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional