You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-09-24 - 02:10
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Sep 23, 2023 12:45:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35845292279186,57sleep10-21swapper/107:09:331
35844902264192,27sleep00-21swapper/007:09:080
3584673991490,1cyclictest0-21swapper/108:22:531
358466999141130,5cyclictest3610955-21kworker/u8:108:22:530
36701002960,4chrt0-21swapper/109:59:161
159199830,16rtkit-daemon0-21swapper/008:44:231
159199830,16rtkit-daemon0-21swapper/008:44:231
159199810,4rtkit-daemon1590-21rtkit-daemon10:45:011
159199810,3rtkit-daemon1590-21rtkit-daemon11:37:291
159199810,3rtkit-daemon1590-21rtkit-daemon09:05:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional