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2025-01-22 - 12:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jan 22, 2025 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
396648423480,7sleep1251rcuc/119:05:281
39673072318274,29sleep00-21swapper/019:09:420
113399570,4rtkit-daemon1132-21rtkit-daemon19:23:530
40593252550,2sleep00-21swapper/022:10:170
40827622490,7sleep00-21swapper/022:42:560
40827622490,7sleep00-21swapper/022:42:550
113399490,4rtkit-daemon1132-21rtkit-daemon00:16:560
113399480,4rtkit-daemon1132-21rtkit-daemon21:06:590
113399480,3rtkit-daemon1132-21rtkit-daemon23:25:440
113399480,10rtkit-daemon0-21swapper/000:34:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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