You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-12 - 12:44
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jul 12, 2025 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21713532260186,25sleep10-21swapper/119:06:001
21715492257181,61sleep00-21swapper/019:08:060
2171839991270,121cyclictest2243542-21sshd21:40:221
2171839991260,120cyclictest2212614-21cpuspeed20:50:151
21718399912396,22cyclictest2296879-21kworker/u8:223:21:221
2171837991231,115cyclictest2278976-21apt-key22:30:030
2171839991211,114cyclictest2337203-21cpuspeed_turbos23:50:281
2171837991190,112cyclictest2284049-21xargs22:35:270
2171839991171,110cyclictest2270493-21sshd22:17:221
2171839991170,111cyclictest2274654-21sh22:24:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional