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2024-04-23 - 22:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Apr 23, 2024 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8295932252186,51sleep00-21swapper/007:08:030
8295622243199,29sleep10-21swapper/107:07:451
82986499231225,4cyclictest831438-21kworker/u8:207:17:480
9877312650,4sleep00-21swapper/011:47:380
159199610,3rtkit-daemon1590-21rtkit-daemon10:56:351
159199590,6rtkit-daemon1590-21rtkit-daemon08:10:130
159199590,4rtkit-daemon1590-21rtkit-daemon12:00:240
159199550,4rtkit-daemon1590-21rtkit-daemon12:25:030
159199550,3rtkit-daemon0-21swapper/109:55:420
159199540,4rtkit-daemon1590-21rtkit-daemon12:23:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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