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2025-07-15 - 12:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jul 15, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30734512280213,51sleep10-21swapper/119:05:271
30743362259183,59sleep00-21swapper/019:08:290
307465099183178,3cyclictest3161454-21kworker/u8:222:08:260
32467202660,5sleep03246506-40mandb00:00:020
125899560,4rtkit-daemon1257-21rtkit-daemon21:19:220
125899550,4rtkit-daemon1257-21rtkit-daemon23:04:400
125899550,4rtkit-daemon1257-21rtkit-daemon20:15:071
32086482540,3sleep00-21swapper/023:07:060
125899530,4rtkit-daemon1257-21rtkit-daemon23:29:551
125899530,3rtkit-daemon1257-21rtkit-daemon00:14:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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