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2023-11-29 - 16:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Wed Nov 29, 2023 12:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12552852284217,45sleep10-21swapper/107:05:281
12563312271205,49sleep00-21swapper/007:07:220
159199690,3rtkit-daemon1590-21rtkit-daemon10:20:001
159199630,4rtkit-daemon1590-21rtkit-daemon09:10:571
159199580,3rtkit-daemon1590-21rtkit-daemon11:09:480
159199550,3rtkit-daemon0-21swapper/011:50:320
159199540,4rtkit-daemon1590-21rtkit-daemon10:53:221
13418002540,4sleep1251rcuc/109:55:211
159199520,4rtkit-daemon1590-21rtkit-daemon09:45:030
159199510,4rtkit-daemon1590-21rtkit-daemon12:03:440
159199510,4rtkit-daemon1590-21rtkit-daemon07:50:101
159199500,3rtkit-daemon0-21swapper/009:45:181
1256686995016,20cyclictest1421748-21ssh11:57:111
159199490,3rtkit-daemon1590-21rtkit-daemon08:16:050
159199480,3rtkit-daemon1590-21rtkit-daemon11:37:460
159199480,12rtkit-daemon1590-21rtkit-daemon08:53:511
14042902460,4sleep01404291-21ssh11:30:420
13344192460,4sleep1251rcuc/109:44:041
1256686994516,15cyclictest1312260-21diskmemload12:00:051
1256686994514,15cyclictest1325664-21ssh09:29:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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