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2024-06-15 - 12:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Jun 15, 2024 00:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1235911730,6ptp4l401ktimersoftd/319:07:503
811521610,5sleep3456899cyclictest21:40:353
41632134112,9sleep00-21swapper/019:08:290
4567999445,7cyclictest33-21ksoftirqd/200:30:302
4567999445,7cyclictest33-21ksoftirqd/200:30:292
4567999331,5cyclictest33-21ksoftirqd/223:55:002
396028113,55sleep10-21swapper/119:05:561
4567998038,10cyclictest33-21ksoftirqd/219:35:152
4567997839,4cyclictest33-21ksoftirqd/223:40:342
57698770,14rtkit-daemon0-21swapper/219:09:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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