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2025-11-11 - 02:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Nov 10, 2025 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3185122310,13sleep30-21swapper/307:05:273
319992207173,22sleep20-21swapper/207:05:392
322002205170,24sleep10-21swapper/107:08:151
322512202168,23sleep00-21swapper/007:08:550
999321640,6sleep23263099cyclictest11:00:212
400421210,2sleep00-21swapper/009:40:240
1365911100,90ptp4l0-21swapper/307:10:013
32629997212,58cyclictest15016-21kworker/1:107:45:441
3262999720,2cyclictest117882sleep107:32:301
32630996631,4cyclictest33-21ksoftirqd/210:00:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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