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2024-07-27 - 06:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Jul 27, 2024 00:46:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1864924150,6sleep00-21swapper/019:05:130
1235911740,6ptp4l401ktimersoftd/319:06:113
1273921620,8sleep02071799cyclictest00:35:300
207209910293,5cyclictest41-21ksoftirqd/322:20:103
207209910091,5cyclictest41-21ksoftirqd/319:15:113
20720999889,5cyclictest41-21ksoftirqd/319:30:113
20720999687,5cyclictest41-21ksoftirqd/300:25:103
20720999583,7cyclictest41-21ksoftirqd/320:25:113
20720999485,5cyclictest41-21ksoftirqd/321:10:093
20720999484,6cyclictest41-21ksoftirqd/323:35:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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