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2025-05-20 - 15:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Tue May 20, 2025 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
182362207173,22sleep20-21swapper/219:09:022
137391207173,23phc2sys0-21swapper/319:09:013
180482203169,23sleep00-21swapper/019:06:390
180422203171,22sleep10-21swapper/119:06:351
1274421740,6sleep21860599cyclictest22:20:172
1465821490,3sleep21860599cyclictest23:30:212
1373918562,15phc2sys0-21swapper/319:10:013
154892560,3sleep00-21swapper/022:25:200
84372540,6sleep11860499cyclictest19:55:211
137291530,1ptp4l391rcuc/320:04:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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