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2024-12-12 - 05:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Thu Dec 12, 2024 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
166582233169,22sleep10-21swapper/119:06:361
137391232167,22phc2sys0-21swapper/319:06:163
168292228169,47sleep20-21swapper/219:08:542
166322204170,23sleep00-21swapper/019:06:160
146092560,2sleep00-21swapper/022:25:250
17213995421,4cyclictest41-21ksoftirqd/320:55:233
17213994920,9cyclictest41-21ksoftirqd/321:35:123
17213994820,9cyclictest41-21ksoftirqd/321:25:233
17213994818,5cyclictest41-21ksoftirqd/323:15:223
17213994516,7cyclictest41-21ksoftirqd/321:08:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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