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2025-07-05 - 21:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Jul 05, 2025 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15992231166,22sleep30-21swapper/307:05:313
19382206172,22sleep10-21swapper/107:08:471
18042205172,22sleep20-21swapper/207:07:072
18352202169,22sleep00-21swapper/007:07:280
413921480,6sleep1233399cyclictest11:40:241
1373918363,11phc2sys0-21swapper/307:10:013
270782710,2sleep00-21swapper/009:09:590
297472690,6sleep0233299cyclictest08:05:200
13852680,2sleep20-21swapper/209:20:282
2335995927,2cyclictest33-21ksoftirqd/209:50:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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