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2024-09-16 - 04:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Sep 16, 2024 00:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123691207184,10phc2sys0-21swapper/319:05:323
1736921090,5sleep10-21swapper/119:05:301
18147999480,9cyclictest33-21ksoftirqd/220:40:122
57698920,15rtkit-daemon0-21swapper/219:09:352
18147998340,6cyclictest33-21ksoftirqd/220:34:592
18147998240,5cyclictest33-21ksoftirqd/200:07:412
18147998068,7cyclictest33-21ksoftirqd/219:10:112
18147998037,6cyclictest33-21ksoftirqd/221:50:232
18147997769,5cyclictest33-21ksoftirqd/200:15:092
18147997639,4cyclictest33-21ksoftirqd/223:20:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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