You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-09-30 - 08:02
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Sep 30, 2023 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
576981230,95rtkit-daemon1281-21mactelnetd19:05:020
1235911160,2ptp4l13143-21bc20:50:213
1235911150,4ptp4l401ktimersoftd/319:06:183
2892729114,18sleep20-21swapper/219:05:052
31298998980,5cyclictest33-21ksoftirqd/222:10:222
31298998880,5cyclictest33-21ksoftirqd/223:30:182
31298998880,5cyclictest33-21ksoftirqd/220:25:182
31298998780,4cyclictest33-21ksoftirqd/223:50:202
31298998779,5cyclictest33-21ksoftirqd/219:25:202
31298998679,4cyclictest33-21ksoftirqd/221:55:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional