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2023-12-07 - 14:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Dec 07, 2023 00:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1541221490,6sleep12737399cyclictest21:00:381
1235911310,105ptp4l401ktimersoftd/319:06:263
26833211694,10sleep10-21swapper/119:08:291
27372999688,5cyclictest9-21ksoftirqd/021:05:190
27372999586,5cyclictest9-21ksoftirqd/023:00:200
27372999384,6cyclictest9-21ksoftirqd/022:35:210
27372999284,5cyclictest9-21ksoftirqd/000:30:200
27372999179,8cyclictest9-21ksoftirqd/023:50:200
27372998773,8cyclictest9-21ksoftirqd/000:15:240
27372998671,8cyclictest9-21ksoftirqd/022:10:200
27372998671,8cyclictest9-21ksoftirqd/022:10:200
2737499831,31cyclictest17147-21/usr/sbin/munin23:25:272
2737499811,26cyclictest29494-21timerandwakeup21:30:352
27372998069,5cyclictest9-21ksoftirqd/022:55:210
27372998039,4cyclictest9-21ksoftirqd/023:40:000
267612803,17sleep20-21swapper/219:07:332
266332781,19sleep00-21swapper/019:05:550
27372997741,8cyclictest9-21ksoftirqd/022:20:000
27372997640,4cyclictest9-21ksoftirqd/020:20:270
27372997540,4cyclictest9-21ksoftirqd/000:40:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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