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2024-06-13 - 03:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Jun 12, 2024 12:46:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2704521750,7sleep3371499cyclictest09:05:483
1432421560,9sleep1371299cyclictest07:30:401
1180121560,21sleep1371299cyclictest10:54:411
1235911110,4ptp4l401ktimersoftd/307:06:493
3714998165,11cyclictest41-21ksoftirqd/308:25:133
3714997661,8cyclictest41-21ksoftirqd/307:15:123
31212755,12sleep10-21swapper/107:06:091
3714997360,8cyclictest41-21ksoftirqd/308:05:133
123591730,1ptp4l401ktimersoftd/308:59:223
3714997255,9cyclictest41-21ksoftirqd/312:10:093
3714996951,9cyclictest41-21ksoftirqd/310:35:103
3714996657,5cyclictest41-21ksoftirqd/307:30:133
3714996450,8cyclictest41-21ksoftirqd/310:10:133
3714996447,9cyclictest41-21ksoftirqd/307:40:133
3714996348,9cyclictest41-21ksoftirqd/307:35:143
3714996347,9cyclictest41-21ksoftirqd/307:55:143
123591610,1ptp4l401ktimersoftd/307:28:273
123591600,1ptp4l401ktimersoftd/310:01:163
3714995946,6cyclictest41-21ksoftirqd/311:20:113
3714995946,6cyclictest41-21ksoftirqd/311:20:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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