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2025-07-02 - 07:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Jul 02, 2025 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
216112230201,20sleep30-21swapper/319:09:593
216092210177,21sleep10-21swapper/119:09:571
214572206175,20sleep00-21swapper/019:07:590
213572204170,23sleep20-21swapper/219:06:482
137391149124,13phc2sys0-21swapper/319:10:013
444921350,8sleep12190699cyclictest19:40:161
2190599583,23cyclictest25900-21dpkg20:25:140
43372560,3sleep00-21swapper/000:10:180
2190599552,27cyclictest20996-21meminfo21:20:220
2190599532,32cyclictest30916-21cut22:50:180
2190599510,32cyclictest2960-21sendmail_mailqu00:05:250
137291500,1ptp4l401ktimersoftd/323:01:523
307742480,1sleep00-21swapper/019:25:270
21908994641,3cyclictest28905-21sh23:55:013
2190599451,21cyclictest24179-21latency_hist19:15:010
2190799442,39cyclictest24056-21cron19:15:002
2190599443,23cyclictest16441-21cat21:10:270
137291440,0ptp4l401ktimersoftd/322:43:343
293192430,2sleep10-21swapper/123:55:191
137291430,0ptp4l401ktimersoftd/322:22:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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