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2025-07-17 - 21:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Jul 17, 2025 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137391234167,22phc2sys0-21swapper/307:09:513
248232206173,22sleep20-21swapper/207:07:432
249682205172,22sleep10-21swapper/107:09:351
248462205172,22sleep00-21swapper/007:08:010
2473321740,6sleep22529999cyclictest09:20:262
137391149125,13phc2sys0-21swapper/307:10:013
2530099725,19cyclictest28026-21latency_hist09:30:013
280652630,4sleep228064-21ls09:30:012
284182610,1sleep20-21swapper/207:15:172
25298995013,2cyclictest25-21ksoftirqd/109:53:171
25298995013,2cyclictest25-21ksoftirqd/109:53:161
309252490,2sleep20-21swapper/207:20:182
2530099480,3cyclictest29686-21taskset07:15:413
25300994630,13cyclictest41-21ksoftirqd/308:56:163
2529899446,11cyclictest25-21ksoftirqd/112:35:171
137291430,0ptp4l401ktimersoftd/310:22:303
2529999421,39cyclictest24339-21kworker/2:111:12:092
2529899421,5cyclictest25-21ksoftirqd/110:15:001
2529899416,3cyclictest25-21ksoftirqd/108:10:201
25298994113,7cyclictest25-21ksoftirqd/112:35:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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