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2025-11-11 - 02:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot2.osadl.org (updated Mon Nov 10, 2025 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3185122310,13sleep30-21swapper/307:05:273
319992207173,22sleep20-21swapper/207:05:392
322002205170,24sleep10-21swapper/107:08:151
322512202168,23sleep00-21swapper/007:08:550
999321640,6sleep23263099cyclictest11:00:212
400421210,2sleep00-21swapper/009:40:240
1365911100,90ptp4l0-21swapper/307:10:013
32629997212,58cyclictest15016-21kworker/1:107:45:441
3262999720,2cyclictest117882sleep107:32:301
32630996631,4cyclictest33-21ksoftirqd/210:00:012
32631996429,4cyclictest41-21ksoftirqd/308:00:003
3262999640,3cyclictest31268-21taskset10:37:331
32630996331,6cyclictest33-21ksoftirqd/207:20:252
32630996130,4cyclictest33-21ksoftirqd/207:25:262
32630996031,4cyclictest33-21ksoftirqd/211:50:192
32630996031,4cyclictest33-21ksoftirqd/207:30:242
32630996028,4cyclictest33-21ksoftirqd/211:57:132
32631995927,7cyclictest41-21ksoftirqd/310:50:193
32630995929,4cyclictest33-21ksoftirqd/209:25:152
32630995927,4cyclictest33-21ksoftirqd/209:10:012
3262999591,26cyclictest533-21gdbus11:57:131
3262899594,17cyclictest19845-21/usr/sbin/munin10:15:240
3262899592,16cyclictest5302-21/usr/sbin/munin12:00:280
32631995828,8cyclictest41-21ksoftirqd/309:25:243
32631995822,3cyclictest41-21ksoftirqd/311:25:153
32631995822,3cyclictest41-21ksoftirqd/307:25:293
32630995827,4cyclictest33-21ksoftirqd/212:35:002
32631995728,8cyclictest41-21ksoftirqd/307:16:403
3262899578,7cyclictest12457-21apt-get07:35:140
32631995623,3cyclictest41-21ksoftirqd/310:40:173
32630995629,3cyclictest33-21ksoftirqd/207:45:152
32630995627,3cyclictest33-21ksoftirqd/210:25:132
32630995627,3cyclictest33-21ksoftirqd/208:05:282
32630995617,10cyclictest33-21ksoftirqd/210:40:302
32631995528,6cyclictest41-21ksoftirqd/310:45:263
32631995525,6cyclictest41-21ksoftirqd/311:00:293
32631995516,10cyclictest41-21ksoftirqd/311:05:273
32630995528,3cyclictest33-21ksoftirqd/210:55:142
32630995528,3cyclictest33-21ksoftirqd/210:30:212
32630995528,3cyclictest33-21ksoftirqd/210:30:212
32630995526,4cyclictest33-21ksoftirqd/209:15:202
32630995526,4cyclictest33-21ksoftirqd/208:30:252
32631995425,4cyclictest41-21ksoftirqd/309:50:163
32631995424,3cyclictest41-21ksoftirqd/312:10:153
32631995420,3cyclictest41-21ksoftirqd/309:10:153
32630995428,4cyclictest33-21ksoftirqd/209:20:202
32630995428,3cyclictest33-21ksoftirqd/208:00:132
32630995427,4cyclictest33-21ksoftirqd/207:10:222
32630995425,4cyclictest33-21ksoftirqd/208:35:222
32630995424,4cyclictest33-21ksoftirqd/208:15:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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