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2024-10-10 - 18:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot2.osadl.org (updated Mon Sep 23, 2024 00:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1212521770,8sleep23245099cyclictest21:50:252
1235911630,6ptp4l401ktimersoftd/319:08:173
318832160138,10sleep10-21swapper/119:06:281
2484821590,8sleep13244999cyclictest22:20:111
2069421550,7sleep33245199cyclictest21:00:203
576981200,18rtkit-daemon0-21swapper/019:09:280
31948210786,9sleep20-21swapper/219:07:142
32451998474,6cyclictest41-21ksoftirqd/320:20:143
32451998336,5cyclictest41-21ksoftirqd/320:02:583
32451998234,5cyclictest41-21ksoftirqd/320:17:403
32451998234,5cyclictest41-21ksoftirqd/320:17:403
32451998233,5cyclictest41-21ksoftirqd/322:36:543
32451998170,6cyclictest41-21ksoftirqd/300:30:053
32451998139,8cyclictest41-21ksoftirqd/321:20:143
32451998038,7cyclictest41-21ksoftirqd/321:55:153
32451997937,8cyclictest41-21ksoftirqd/300:25:253
32451997935,8cyclictest41-21ksoftirqd/322:30:283
32451997841,7cyclictest41-21ksoftirqd/319:45:283
32451997736,8cyclictest41-21ksoftirqd/320:50:303
32451997734,8cyclictest41-21ksoftirqd/323:00:193
32451997637,6cyclictest41-21ksoftirqd/322:15:293
32451997568,4cyclictest41-21ksoftirqd/319:30:063
32451997532,8cyclictest41-21ksoftirqd/320:30:253
32451997436,4cyclictest41-21ksoftirqd/319:40:153
32451997435,11cyclictest41-21ksoftirqd/319:21:363
32451997434,8cyclictest41-21ksoftirqd/321:45:223
32451997434,8cyclictest41-21ksoftirqd/321:45:213
32451997334,5cyclictest41-21ksoftirqd/323:30:203
32451997332,7cyclictest41-21ksoftirqd/321:50:283
32451997332,10cyclictest41-21ksoftirqd/323:15:003
252942730,5sleep2311rcuc/222:20:162
32451997238,4cyclictest41-21ksoftirqd/323:05:013
32451997232,8cyclictest41-21ksoftirqd/300:12:233
32451997134,9cyclictest41-21ksoftirqd/319:15:253
32451997133,11cyclictest41-21ksoftirqd/321:30:163
32451997129,10cyclictest41-21ksoftirqd/323:59:563
32451997129,10cyclictest41-21ksoftirqd/320:58:023
32451997037,7cyclictest41-21ksoftirqd/322:40:213
32451997035,4cyclictest41-21ksoftirqd/322:01:103
32451997035,10cyclictest41-21ksoftirqd/322:05:203
32451996936,4cyclictest41-21ksoftirqd/323:35:293
32451996935,4cyclictest41-21ksoftirqd/320:07:023
32451996931,9cyclictest41-21ksoftirqd/319:25:153
32451996831,5cyclictest41-21ksoftirqd/320:40:333
32451996829,9cyclictest41-21ksoftirqd/320:47:413
32451996828,9cyclictest41-21ksoftirqd/300:08:473
32451996730,9cyclictest41-21ksoftirqd/300:19:263
32451996730,5cyclictest41-21ksoftirqd/321:43:583
32451996728,5cyclictest41-21ksoftirqd/322:57:133
32451996726,9cyclictest41-21ksoftirqd/323:19:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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